Searched +full:strobe +full:- +full:sel (Results 1 – 9 of 9) sorted by relevance
7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt11 - compatible: should be one of:12 "ti,am654-sdhci-5.1": SDHCI on AM654 device.13 "ti,j721e-sdhci-8bit": 8 bit SDHCI on J721E device.14 "ti,j721e-sdhci-4bit": 4 bit SDHCI on J721E device.15 - reg: Must be two entries.16 - The first should be the sdhci register space17 - The second should the subsystem/phy register space18 - clocks: Handles to the clock inputs.[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/4 ---5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#11 - Ulf Hansson <ulf.hansson@linaro.org>14 - $ref: sdhci-common.yaml#19 - enum:20 - ti,am62-sdhci21 - ti,am64-sdhci-4bit[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/9 serdes_refclk: serdes-refclk {10 #clock-cells = <0>;11 compatible = "fixed-clock";17 compatible = "mmio-sra[all...]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/8 #include <dt-bindings/phy/phy-cadence.h>9 #include <dt-bindings/phy/phy-t[all...]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/8 #include <dt-bindings/mux/mux.h>9 #include <dt-bindings/phy/phy.h>10 #include <dt-bindings/phy/phy-t[all...]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)5 * Copyright 2016-2017 Google, Inc8 #include <dt-bindings/input/input.h>9 #include "rk3399-op1.dtsi"18 stdout-path = "serial2:115200n8";27 * - Rails that only connect to the EC (or devices that the EC talks to)29 * - Rails _are_ included if the rails go to the AP even if the AP38 * - Th[all...]
1 /*-2 * SPDX-License-Identifier: ISC4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting5 * Copyright (c) 2002-2008 Atheros Communications, Inc.34 #define AR_WA 0x4004 /* PCIE work-arounds */120 /* RTC_DERIVED_* - only for AR9130 */149 #define AR_TXOP_X 0x81ec /* txop for legacy non-qos */154 /* generic timers based on tsf - all uS */208 #define AR_GTTM_USEC 0x00000001 // usec strobe211 #define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe[all …]
32 /* MAC Control Register - only write values of 1 have effect */37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)55 /* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */124 #define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame144 #define AR_MIBC_MCS 0x00000008 // MIB counter strobe increment all211 #define AR_GTTM_USEC 0x00000001 // usec strobe214 #define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe238 #define AR_ISR_HP_RXOK 0x00000001 // At least one frame rx on high-priority queue sans errors239 #define AR_ISR_LP_RXOK 0x00000002 // At least one frame rx on low-priority queue sans errors[all …]
2 * Copyright (c) 2017-2018 Cavium, Inc. 78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…116 … (0x1<<9) // Fast back-to-back transaction ena…128 … (0x1<<23) // Fast back-to-back capable. Not ap…145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…[all …]