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/freebsd-src/sys/arm/mv/
H A Dmvebu_pinctrl.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
62 const struct mv_pins *pins; member
67 {"mpp0", {"gpio", "sdio", NULL, "spi0"}},
68 {"mpp1", {"gpio", "sdio", NULL, "spi0"}},
69 {"mpp2", {"gpio", "sdio", NULL, "spi0"}},
70 {"mpp3", {"gpio", "sdio", NULL, "spi0"}},
76 {"mpp9", {"gpio", "sdio", NULL, "spi0"}},
91 .pins = ap806_pins,
102 {"marvell,ap806-pinctrl", (uintptr_t)&ap806_padconf},
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-cc
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H A Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
12 /dts-v1/;
15 #include "zynqmp-clk-ccf.dtsi"
16 #include <dt-bindings/input/input.h>
17 #include <dt-binding
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/freebsd-src/sys/contrib/device-tree/src/arm64/toshiba/
H A Dtmpv7708_pins.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 spi0_pins: spi0-pins {
5 function = "spi0";
8 spi1_pins: spi1-pins {
12 spi2_pins: spi2-pins {
16 spi3_pins: spi3-pins {
20 spi4_pins: spi4-pins {
24 spi5_pins: spi5-pins {
28 spi6_pins: spi6-pins {
32 uart0_pins: uart0-pins {
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/pinctrl/
H A Dmarvell,armada-xp-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9 - reg: register specifier of MPP registers
13 Available mpp pins/groups and functions:
19 name pins functions
50 mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk)
57 mpp36 36 gpio, spi0(mosi)
58 mpp37 37 gpio, spi0(miso)
59 mpp38 38 gpio, spi0(sck)
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H A Dtoshiba,visconti-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
18 - toshiba,tmpv7708-pinctrl
24 - $ref: pinctrl.yaml#
27 - compatible
28 - reg
31 '-pins$':
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H A Dmarvell,armada-370-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
14 name pins functions
20 mpp4 4 gpio, vdd(cpu-pd)
27 mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
34 spi0(cs2)
36 spi0(cs3)
53 mpp32 32 gpio, spi0(cs0)
[all …]
H A Dmediatek,mt7986-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
13 The MediaTek's MT7986 Pin controller is used to control SoC pins.
18 - mediatek,mt7986a-pinctrl
19 - mediatek,mt7986b-pinctrl
25 reg-names:
27 - const: gpio
[all …]
H A Dmarvell,armada-38x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
8 "marvell,88f6828-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
16 name pins functions
30 mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq)
31 mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pci…
32 mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq)
33 mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi)
[all …]
H A Dmarvell,armada-375-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6720-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
14 name pins functions
16 mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
17 mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
20 mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
21 mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
24 mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
[all …]
H A Dmarvell,armada-39x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
16 name pins functions
33 mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck)
34 mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda)
35 mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio)
36 mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck)
[all …]
H A Dmediatek,mt7981-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Golle <daniel@makrotopia.org>
13 The MediaTek's MT7981 Pin controller is used to control SoC pins.
18 - mediatek,mt7981-pinctrl
24 reg-names:
26 - const: gpio
27 - const: iocfg_rt
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/microchip/
H A Dat91-q5xr5.dts1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
24 #address-cells = <1>;
25 #size-cells = <1>;
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <18432000>;
34 clock-frequency = <32768>;
38 clock-frequency = <18432000>;
51 compatible = "cfi-flash";
52 #address-cells = <1>;
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/nuvoton/
H A Dnuvoton-npcm730-kudo.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
5 #include "nuvoton-npcm730.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
34 spi0 = &spi0;
41 stdout-path = &serial3;
48 iio-hwmo
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/freebsd-src/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
[all …]
H A Drk3066a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
22 #address-cell
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H A Drk322x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-binding
419 spi0: spi@11090000 { global() label
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/freebsd-src/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3399-rock960.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3399-rock960.dtsi"
14 stdout-path = "serial2:1500000n8";
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>,
24 user_led1: led-1 {
27 linux,default-trigger = "heartbeat";
30 user_led2: led-2 {
[all …]
H A Drk3368.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controlle
236 spi0: spi@ff110000 { global() label
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-370.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 #include "armada-370-xp.dtsi"
18 #address-cells = <1>;
19 #size-cells = <1>;
22 compatible = "marvell,armada370", "marvell,armada-370-xp";
31 compatible = "marvell,armada370-mbus", "simple-bus";
39 compatible = "marvell,armada-370-pcie";
43 #address-cells = <3>;
[all …]
H A Darmada-xp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 #include "armada-370-xp.dtsi"
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
38 internal-regs {
40 compatible = "marvell,armada-xp-sdram-controller";
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am65-iot2050-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) Siemens AG, 2018-2024
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/net/ti-dp83867.h>
28 spi0
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/freebsd-src/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7986b-rfb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
12 chassis-type = "embedded";
13 compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
20 stdout-path = "serial0:115200n8";
37 compatible = "mediatek,eth-mac";
39 phy-mode = "2500base-
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/freebsd-src/sys/contrib/device-tree/src/arm64/socionext/
H A Duniphier-pxs3-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 /dts-v1/;
9 #include "uniphier-pxs3.dtsi"
10 #include "uniphier-support-card.dtsi"
14 compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
17 stdout-path = "serial0:115200n8";
30 spi0 = &spi0;
50 &spi0 {
71 xirq4-hog {
72 gpio-hog;
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam335x-sancloud-bbe-lite.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
9 #include "am335x-bone-common.dtsi"
10 #include "am335x-boneblack-commo
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