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Searched +full:soc +full:- +full:ctl +full:- +full:syscon (Results 1 – 12 of 12) sorted by relevance

/freebsd-src/sys/contrib/device-tree/Bindings/mmc/
H A Darasan,sdhci.txt7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
9 [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
12 - compatible: Compatibility string. One of:
13 - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
14 - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
15 - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
16 - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
17 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
18 - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
[all …]
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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/freebsd-src/sys/contrib/device-tree/Bindings/reset/
H A Dhisilicon,hi6220-reset.txt7 The reset controller registers are part of the system-ctl block on
8 hi6220 SoC.
11 - compatible: should be one of the following:
12 - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
13 - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
14 - "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller.
15 - reg: should be register base and length as documented in the
17 - #reset-cells: 1, see below
21 compatible = "hisilicon,hi6220-sysctrl", "syscon";
23 #clock-cells = <1>;
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/freebsd-src/sys/arm64/rockchip/
H A Drk3399_emmcphy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <dev/syscon/syscon.h>
102 { "rockchip,rk3399-emmc-phy", 1 },
107 struct syscon *syscon; member
112 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask))
150 SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON6, in rk_emmcphy_enable()
156 SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON0, in rk_emmcphy_enable()
163 SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON6, (mask << 16) | val); in rk_emmcphy_enable()
168 sc->phy_conf = (struct rk_emmcphy_conf *)ofw_bus_search_compatible(dev, in rk_emmcphy_enable()
[all …]
/freebsd-src/sys/dev/sdhci/
H A Dsdhci_fdt.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
55 #include <dev/syscon/syscon.h>
112 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask))
116 { "marvell,armada-380-sdhc
147 struct syscon *syscon; /* Handle to the syscon */ global() member
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/freebsd-src/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controlle
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/freebsd-src/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-binding
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/freebsd-src/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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/freebsd-src/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-binding
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H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-binding
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/freebsd-src/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
6 #include "rk3399-base.dtsi"
9 cluster0_opp: opp-table-0 {
10 compatible = "operating-points-v2";
11 opp-share
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