Searched +full:sgmii +full:- +full:rxclk +full:- +full:falling +full:- +full:edge (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - John Crispin <john@phrozen.org>13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in18 PHY it is connected to. In this config, an internal mdio-bus is registered and20 mdio-bus configurations are not supported by the hardware.27 - enum:28 - qca,qca8327[all …]
2 * Copyright (c) 2017-2018 Cavium, Inc. 78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…116 … (0x1<<9) // Fast back-to-back transaction ena…128 … (0x1<<23) // Fast back-to-back capable. Not ap…145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…[all …]