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/freebsd-src/sys/contrib/device-tree/Bindings/usb/
H A Dgpio-sbu-mux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/gpio-sb
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/freebsd-src/sys/contrib/device-tree/Bindings/sound/
H A Dak4458.txt7 - compatible : "asahi-kasei,ak4458" or "asahi-kasei,ak4497"
8 - reg : The I2C address of the device for I2C
11 - reset-gpios: A GPIO specifier for the power down & reset pin
12 - mute-gpios: A GPIO specifier for the soft mute pin
13 - AVDD-supply: Analog power supply
14 - DVDD-supply: Digital power supply
15 - dsd-path: Select DSD input pins for ak4497
16 0: select #16, #17, #19 pins
17 1: select #3, #4, #5 pins
23 compatible = "asahi-kasei,ak4458";
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H A Dasahi-kasei,ak4458.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/sound/asahi-kasei,ak4458.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
15 - asahi-kasei,ak4458
16 - asahi-kasei,ak4497
21 avdd-supply:
24 dvdd-supply:
27 reset-gpios:
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H A Dsimple-audio-mux.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-audio-mu
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/freebsd-src/sys/contrib/device-tree/Bindings/spi/
H A Dfsl-spi.txt4 - cell-index : QE SPI subblock index.
7 - compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
8 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
9 - reg : Offset and length of the register set for the device
10 - interrupts : <a b> where a is the interrupt number and b is a
15 - clock-frequency : input clock frequency to non FSL_SOC cores
18 - cs-gpios : specifies the gpio pins to be used for chipselects.
19 The gpios will be referred to as reg = <index> in the SPI child nodes.
20 If unspecified, a single SPI device without a chip select can be used.
21 - fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the
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H A Dqcom,spi-qup.txt4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
10 - compatible: Should contain:
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
15 - reg: Should contain base register location and length
16 - interrupts: Interrupt number used by this controller
18 - clocks: Should contain the core clock and the AHB clock.
19 - clock-names: Should be "core" for the core clock and "iface" for the
22 - #address-cells: Number of cells required to define a chip select
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H A Dspi-samsung.txt8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
18 - interrupts: The interrupt number to the cpu. The interrupt specifier format
21 - dmas : Two or more DMA channel specifiers following the convention outlined
24 - dma-names: Names for the dma channels. There must be at least one channel
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H A Dspi-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-GPIO
10 - Rob Herring <robh@kernel.org>
13 This represents a group of 3-n GPIO lines used for bit-banged SPI on
17 - $ref: /schemas/spi/spi-controller.yaml#
21 const: spi-gpio
23 sck-gpios:
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/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dgpio-mux-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/gpio-mux-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergej Sawazki <ce3a@gmx.de>
14 const: gpio-mux-clock
18 - description: First parent clock
19 - description: Second parent clock
21 '#clock-cells':
24 select-gpios:
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H A Dgpio-mux-clock.txt5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be "gpio-mux-clock".
9 - clocks: list of two references to parent clocks.
10 - #clock-cells : from common clock binding; shall be set to 0.
11 - select-gpios : GPIO reference for selecting the parent clock.
15 compatible = "gpio-mux-clock";
17 #clock-cells = <0>;
18 select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dsff,sfp.txt1 Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
6 - compatible : must be one of
10 - i2c-bus : phandle of an I2C bus controller for the SFP two wire serial
15 - mod-def0-gpios : GPIO phandle and a specifier of the MOD-DEF0 (AKA Mod_ABS)
19 - los-gpios : GPIO phandle and a specifier of the Receiver Loss of Signal
22 - tx-fault-gpios : GPIO phandle and a specifier of the Module Transmitter
25 - tx-disable-gpios : GPIO phandle and a specifier of the Transmitter Disable
28 - rate-select0-gpios : GPIO phandle and a specifier of the Rx Signaling Rate
29 Select (AKA RS0) output gpio signal, low: low Rx rate, high: high Rx rate
32 - rate-select1-gpios : GPIO phandle and a specifier of the Tx Signaling Rate
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H A Dsff,sfp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd-src/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp-lenovo-ix4-300d.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for Lenovo Iomega ix4-300d
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "armada-xp-mv78230.dtsi"
15 model = "Lenovo Iomega ix4-300d";
16 compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230",
17 "marvell,armadaxp", "marvell,armada-370-xp";
20 stdout-path = "serial0:115200n8";
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H A Dkirkwood-openrd.dtsi1 // SPDX-License-Identifier: GPL-2.0
12 #include "kirkwood-6281.dtsi"
22 stdout-path = &uart0;
26 pinctrl: pin-controller@10000 {
27 pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>;
28 pinctrl-names = "default";
30 pmx_select28: pmx-select-rs232-rs485 {
34 pmx_sdio_cd: pmx-sdio-cd {
38 pmx_select34: pmx-select-uart-sd {
49 nr-ports = <2>;
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/freebsd-src/sys/contrib/device-tree/Bindings/iio/resolver/
H A Dadi,ad2s1210.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD2S1210 Resolver-to-Digital Converter
10 - Michael Hennerich <michael.hennerich@analog.com>
13 The AD2S1210 is a complete 10-bit to 16-bit resolution tracking
14 resolver-to-digital converter, integrating an on-board programmable
29 0 0 Normal mode - position output
30 0 1 Normal mode - velocity output
44 Note on SPI connections: The CS line on the AD2S1210 should hard-wired to
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/freebsd-src/sys/contrib/device-tree/Bindings/mtd/
H A Dfsl-upm-nand.txt4 - compatible : "fsl,upm-nand".
5 - reg : should specify localbus chip select and size used for the chip.
6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offse
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H A Dnand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
21 pattern: "^nand-controller(@.*)?"
23 "#address-cells":
26 "#size-cells":
31 cs-gpios:
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/freebsd-src/sys/contrib/device-tree/Bindings/misc/
H A Difm-csi.txt4 - compatible: "ifm,o2d-csi"
5 - reg: specifies sensor chip select number and associated address range
6 - interrupts: external interrupt line number and interrupt sense mode
8 - gpios: three gpio-specifiers for "capture", "reset" and "master enable"
9 GPIOs (strictly in this order).
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
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H A Deeprom-93xx46.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/eeprom-93xx46.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cory Tusar <cory.tusar@pid1solutions.com>
15 - atmel,at93c46
16 - atmel,at93c46d
17 - atmel,at93c56
18 - atmel,at93c66
19 - eeprom-93xx46
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H A Deeprom-93xx46.txt4 - compatible : shall be one of:
9 "eeprom-93xx46"
11 - data-size : number of data bits per word (either 8 or 16)
14 - read-only : parameter-less property which disables writes to the EEPROM
15 - select-gpios : if present, specifies the GPIO that will be asserted prior to
18 Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt
19 apply. In particular, "reg" and "spi-max-frequency" properties must be given.
23 compatible = "eeprom-93xx46";
25 spi-max-frequency = <1000000>;
26 spi-cs-high;
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/freebsd-src/sys/contrib/device-tree/Bindings/eeprom/
H A Dmicrochip,93lc46b.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cory Tusar <cory.tusar@pid1solutions.com>
15 - atmel,at93c46
16 - atmel,at93c46d
17 - atmel,at93c56
18 - atmel,at93c66
19 - eeprom-93xx46
20 - microchip,93lc46b
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/freebsd-src/sys/contrib/device-tree/Bindings/regulator/
H A Drichtek,rt6245-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rt6245-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
13 The RT6245 is a high-performance, synchronous step-down converter
18 - $ref: regulator.yaml#
23 - richtek,rt6245
28 enable-gpios:
31 it will be treat as a default-on power.
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/freebsd-src/sys/contrib/device-tree/Bindings/gpio/
H A Dspear_spics.txt10 Chipselects can be controlled by software by turning them as GPIOs. SPEAr
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
25 * #gpio-cells: should be 1 and will mention chip select number
30 -------
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H A Dgpio-consumer-common.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-consumer-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <brgl@bgdev.pl>
11 - Linus Walleij <linus.walleij@linaro.org>
14 Pay attention to using proper GPIO flag (e.g. GPIO_ACTIVE_LOW) for the GPIOs
17 select: true
20 enable-gpios:
25 reset-gpios:
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/freebsd-src/sys/contrib/device-tree/Bindings/fpga/
H A Daltera-passive-serial.txt11 - compatible: Must be one of the following:
12 "altr,fpga-passive-serial",
13 "altr,fpga-arria10-passive-serial"
14 - reg: SPI chip select of the FPGA
15 - nconfig-gpios: config pin (referred to as nCONFIG in the manual)
16 - nstat-gpios: status pin (referred to as nSTATUS in the manual)
19 - confd-gpios: confd pin (referred to as CONF_DONE in the manual)
23 compatible = "altr,fpga-passive-serial";
24 spi-max-frequency = <20000000>;
26 nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
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