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/freebsd-src/sys/contrib/device-tree/Bindings/arm/bcm/
H A Dbrcm,bcm63138.txt1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
11 An optional Boot lookup table Device Tree node is required for secondary CPU
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
16 Required properties for the Boot lookup table node:
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
21 - enable-method: should be "brcm,bcm63138"
[all …]
/freebsd-src/sys/contrib/device-tree/src/powerpc/
H A Dxpedite5301.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
28 #address-cells = <1>;
29 #size-cells = <0>;
33 reg = <0x0>;
34 d-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxpedite5330.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #address-cells = <1>;
30 #size-cells = <0>;
33 cell-index = <0>;
37 * module-present;
[all …]
H A Dxpedite5370.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XPedite5370 3U VPX single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 reg = <0x0>;
32 d-cache-line-size = <32>; // 32 bytes
33 i-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 reg = <0x0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxpedite5200.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
34 reg = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5200_xmon.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 * xMon boot loader memory map which differs from U-Boot's.
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 form-factor = "PMC/XMC";
18 boot-bank = <0x0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
38 reg = <0>;
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm-nsp-ax.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom Northstar Plus Ax stepping-specific bindings.
4 * Notable differences from B0+ are the secondary-boot-reg and
9 secondary-boot-reg = <0xffff042c>;
13 /delete-property/ dma-coherent;
17 /delete-property/ dma-coherent;
21 /delete-property/ dma-coherent;
25 /delete-property/ dma-coherent;
29 /delete-property/ dma-coherent;
33 /delete-property/ dma-coherent;
[all …]
H A Dbcm23550.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
8 #include "bcm2166x-common.dtsi"
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
20 reg
[all...]
H A Dbcm4708.dtsi5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
20 stdout-path = "serial0:115200n8";
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "brcm,bcm-nsp-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
32 reg = <0x0>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-lx2160a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/mstar/
H A Dmstar,smpctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Daniel Palmer <daniel@thingy.jp>
15 have a region of registers that allow setting the boot address
16 and a magic number that allows secondary processors to leave
17 the loop they are parked in by the boot ROM.
22 - enum:
23 - sstar,ssd201-smpctrl # SSD201/SSD202D
24 - const: mstar,smpctrl
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/openrisc/opencores/
H A Dor1ksim.txt6 specification, however some aspects, such as the boot protocol have been defined
10 -------------------
11 - compatible: Must include "opencores,or1ksim"
14 ----------
16 - #address-cells: Must be 1.
17 - #size-cells: Must be 0.
18 A CPU sub-node is also required for at least CPU 0. Since the topology may
19 be probed via CPS, it is not necessary to specify secondary CPUs. Required
21 - compatible: Must be "opencores,or1200-rtlsvn481".
22 - reg: CPU number.
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bi
[all...]
H A Dsyna.txt3 According to https://www.synaptics.com/company/news/conexant-marvell
7 ---------
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm/hisilicon/
H A Dhip01-ca9x2.dts1 // SPDX-License-Identifier: GPL-2.0-only
11 /dts-v1/;
13 /* First 8KB reserved for secondary core boot */
20 compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01";
23 #address-cells = <1>;
24 #size-cells = <0>;
25 enable-method = "hisilicon,hip01-smp";
29 compatible = "arm,cortex-a9";
30 reg = <0>;
35 compatible = "arm,cortex-a9";
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/mfd/
H A Dti,tps6594.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd-src/sys/dts/arm/
H A Dsocfpga_arria10_socdk_sdmmc.dts1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
31 /dts-v1/;
36 compatible = "altr,socfpga-arria10", "altr,socfpga";
38 /* Reserve first page for secondary CPU trampoline code */
44 clock-frequency = <200000000>;
49 compatible = "arm,cortex-a9-global-timer";
50 reg = <0xffffc200 0x20>;
52 clock-frequency = <200000000>;
63 clock-frequency = < 50000000 >;
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/mips/img/
H A Dpistachio.txt5 --------------------
6 - compatible: Must include "img,pistachio".
9 ----------
11 - #address-cells: Must be 1.
12 - #size-cells: Must be 0.
13 A CPU sub-node is also required for at least CPU 0. Since the topology may
14 be probed via CPS, it is not necessary to specify secondary CPUs. Required
16 - device_type: Must be "cpu".
17 - compatible: Must be "mti,interaptiv".
18 - reg: CPU number.
[all …]
/freebsd-src/sys/arm/rockchip/
H A Drk32xx_mp.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
74 mp_maxid = ncpu - 1; in rk32xx_mp_setmaxid()
92 /* Power off all secondary cores first */ in rk32xx_mp_start_pmu()
99 /* Power up all secondary cores */ in rk32xx_mp_start_pmu()
120 rk32xx_start_ap(u_int id, phandle_t node, u_int addr_cells, pcell_t *reg) in rk32xx_start_ap() argument
129 /* Skip boot CPU. */ in rk32xx_start_ap()
137 mask = 1 << (*reg & 0x0f); in rk32xx_start_ap()
142 *reg, id); in rk32xx_start_ap()
144 rv = OF_getprop(node, "enable-method", method, sizeof(method)); in rk32xx_start_ap()
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/arm/
H A Darm-realview-eb-mp.dtsi23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "arm-realview-eb.dtsi"
30 * and Cortex-A9 MPCore.
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "arm,realview-eb-so
[all...]
H A Dintegratorap.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "arm,integrator-ap";
16 #address-cells = <1>;
17 #size-cells = <0>;
24 * boot loade
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/hisilicon/
H A Dhisilicon.txt2 ----------------------------------------------------
5 - compatible = "hisilicon,hi3660";
9 - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
13 - compatible = "hisilicon,hi3670";
17 - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
21 - compatible = "hisilicon,hi3798cv200";
25 - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
29 - compatible = "hisilicon,hi3620-hi4511";
33 - compatible = "hisilicon,hi6220";
37 - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8994-sony-xperia-kitakami.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/gpio-keys.h>
18 * and requires driver-side changes (including CPR, be warned!!).
21 qcom,msm-id = <207 0x20000>, <207 0x20001>;
23 qcom,pmic-i
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/
H A Dchosen.txt2 ---------------
5 for passing data between firmware and the operating system, like boot
11 kaslr-seed
12 -----------
22 kaslr-seed = <0xfeedbeef 0xc0def00d>;
31 stdout-path
32 -----------
34 Device trees may specify the device to be used for boot console output
35 with a stdout-path property under /chosen, as described in the Devicetree
40 stdout-path = "/serial@f00:115200";
[all …]

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