Searched +full:sdfec +full:- +full:code (Results 1 – 1 of 1) sorted by relevance
1 * Xilinx SDFEC(16nm) IP *3 The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block4 which provides high-throughput LDPC and Turbo Code implementations.6 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality12 - compatible: Must be "xlnx,sd-fec-1.1"13 - clock-names : List of input clock names from the following:14 - "core_clk", Main processing clock for processing core (required)15 - "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required)16 - "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)17 - "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)[all …]