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Searched full:sdclk (Results 1 – 7 of 7) sorted by relevance

/freebsd-src/sys/contrib/device-tree/Bindings/mmc/
H A Dcdns,sdhci.yaml92 cdns,phy-dll-delay-sdclk:
94 Value of the delay introduced on the sdclk output for all modes except
100 cdns,phy-dll-delay-sdclk-hsmmc:
102 Value of the delay introduced on the sdclk output for HS200, HS400 and
155 cdns,phy-dll-delay-sdclk = <0>;
H A Dmarvell,xenon-sdhci.txt132 clocks = <&sdclk>, <&axi_clk>;
168 clocks = <&sdclk>;
H A Dmarvell,xenon-sdhci.yaml232 clocks = <&sdclk 0>, <&axi_clk 0>;
274 clocks = <&sdclk 0>;
/freebsd-src/sys/contrib/device-tree/src/arm64/socionext/
H A Duniphier-ld11.dtsi464 cdns,phy-dll-delay-sdclk = <21>;
465 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
H A Duniphier-pxs3.dtsi422 cdns,phy-dll-delay-sdclk = <21>;
423 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
H A Duniphier-ld20.dtsi602 cdns,phy-dll-delay-sdclk = <21>;
603 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
/freebsd-src/sys/dev/rtsx/
H A Drtsx.c1830 * Set or change SDCLK frequency or disable the SD clock.