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/llvm-project/llvm/test/CodeGen/VE/Scalar/
H A Dconstants.ll7 ; CHECK-NEXT: b.l.t (, %s10)
15 ; CHECK-NEXT: b.l.t (, %s10)
23 ; CHECK-NEXT: b.l.t (, %s10)
31 ; CHECK-NEXT: b.l.t (, %s10)
39 ; CHECK-NEXT: b.l.t (, %s10)
47 ; CHECK-NEXT: b.l.t (, %s10)
55 ; CHECK-NEXT: b.l.t (, %s10)
63 ; CHECK-NEXT: b.l.t (, %s10)
71 ; CHECK-NEXT: b.l.t (, %s10)
79 ; CHECK-NEXT: b.l.t (, %s10)
[all …]
H A Dcast.ll7 ; CHECK-NEXT: b.l.t (, %s10)
16 ; CHECK-NEXT: b.l.t (, %s10)
24 ; CHECK-NEXT: b.l.t (, %s10)
33 ; CHECK-NEXT: b.l.t (, %s10)
42 ; CHECK-NEXT: b.l.t (, %s10)
52 ; CHECK-NEXT: b.l.t (, %s10)
62 ; CHECK-NEXT: b.l.t (, %s10)
72 ; CHECK-NEXT: b.l.t (, %s10)
82 ; CHECK-NEXT: b.l.t (, %s10)
92 ; CHECK-NEXT: b.l.t (, %s10)
[all...]
H A Dsymbol_relocation_tls.ll19 ; GENDYN-NEXT: sic %s10
20 ; GENDYN-NEXT: lea.sl %s0, (%s10, %s0)
25 ; GENDYN-NEXT: lea.sl %s12, (%s10, %s12)
27 ; GENDYN-NEXT: bsic %s10, (, %s12)
39 ; GENDYNPIC-NEXT: sic %s10
40 ; GENDYNPIC-NEXT: lea.sl %s0, (%s10, %s0)
45 ; GENDYNPIC-NEXT: lea.sl %s12, (%s10, %s12)
47 ; GENDYNPIC-NEXT: bsic %s10, (, %s12)
58 ; GENDYN-NEXT: sic %s10
59 ; GENDYN-NEXT: lea.sl %s0, (%s10, %s0)
[all …]
H A Dtls.ll17 ; GENDYN-NEXT: sic %s10
18 ; GENDYN-NEXT: lea.sl %s0, x@tls_gd_hi(%s10, %s0)
21 ; GENDYN-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
22 ; GENDYN-NEXT: bsic %s10, (, %s12)
33 ; GENDYNPIC-NEXT: sic %s10
34 ; GENDYNPIC-NEXT: lea.sl %s0, x@tls_gd_hi(%s10, %s0)
37 ; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
38 ; GENDYNPIC-NEXT: bsic %s10, (, %s12)
58 ; GENDYN-NEXT: sic %s10
59 ; GENDYN-NEXT: lea.sl %s0, y@tls_gd_hi(%s10, %s0)
[all …]
H A Dmin.ll12 ; CHECK-NEXT: b.l.t (, %s10)
17 ; OPT-NEXT: b.l.t (, %s10)
29 ; CHECK-NEXT: b.l.t (, %s10)
34 ; OPT-NEXT: b.l.t (, %s10)
46 ; CHECK-NEXT: b.l.t (, %s10)
51 ; OPT-NEXT: b.l.t (, %s10)
63 ; CHECK-NEXT: b.l.t (, %s10)
68 ; OPT-NEXT: b.l.t (, %s10)
80 ; CHECK-NEXT: b.l.t (, %s10)
85 ; OPT-NEXT: b.l.t (, %s10)
[all...]
H A Dmax.ll12 ; CHECK-NEXT: b.l.t (, %s10)
17 ; OPT-NEXT: b.l.t (, %s10)
29 ; CHECK-NEXT: b.l.t (, %s10)
34 ; OPT-NEXT: b.l.t (, %s10)
47 ; CHECK-NEXT: b.l.t (, %s10)
52 ; OPT-NEXT: b.l.t (, %s10)
65 ; CHECK-NEXT: b.l.t (, %s10)
70 ; OPT-NEXT: b.l.t (, %s10)
82 ; CHECK-NEXT: b.l.t (, %s10)
87 ; OPT-NEXT: b.l.t (, %s10)
[all...]
H A Dxor.ll7 ; CHECK-NEXT: b.l.t (, %s10)
16 ; CHECK-NEXT: b.l.t (, %s10)
25 ; CHECK-NEXT: b.l.t (, %s10)
35 ; CHECK-NEXT: b.l.t (, %s10)
44 ; CHECK-NEXT: b.l.t (, %s10)
53 ; CHECK-NEXT: b.l.t (, %s10)
62 ; CHECK-NEXT: b.l.t (, %s10)
71 ; CHECK-NEXT: b.l.t (, %s10)
80 ; CHECK-NEXT: b.l.t (, %s10)
89 ; CHECK-NEXT: b.l.t (, %s10)
[all …]
H A Dfp_extload_truncstore.ll14 ; CHECK-NEXT: st %s10, 8(, %s11)
32 ; CHECK-NEXT: bsic %s10, (, %s12)
34 ; CHECK-NEXT: ld %s10, 8(, %s11)
36 ; CHECK-NEXT: b.l.t (, %s10)
46 ; CHECK-NEXT: st %s10, 8(, %s11)
64 ; CHECK-NEXT: bsic %s10, (, %s12)
67 ; CHECK-NEXT: ld %s10, 8(, %s11)
69 ; CHECK-NEXT: b.l.t (, %s10)
79 ; CHECK-NEXT: st %s10, 8(, %s11)
97 ; CHECK-NEXT: bsic %s10, (, %s12)
[all …]
H A Dor.ll7 ; CHECK-NEXT: b.l.t (, %s10)
16 ; CHECK-NEXT: b.l.t (, %s10)
25 ; CHECK-NEXT: b.l.t (, %s10)
35 ; CHECK-NEXT: b.l.t (, %s10)
44 ; CHECK-NEXT: b.l.t (, %s10)
53 ; CHECK-NEXT: b.l.t (, %s10)
62 ; CHECK-NEXT: b.l.t (, %s10)
71 ; CHECK-NEXT: b.l.t (, %s10)
80 ; CHECK-NEXT: b.l.t (, %s10)
89 ; CHECK-NEXT: b.l.t (, %s10)
[all …]
H A Dand.ll7 ; CHECK-NEXT: b.l.t (, %s10)
16 ; CHECK-NEXT: b.l.t (, %s10)
25 ; CHECK-NEXT: b.l.t (, %s10)
35 ; CHECK-NEXT: b.l.t (, %s10)
44 ; CHECK-NEXT: b.l.t (, %s10)
53 ; CHECK-NEXT: b.l.t (, %s10)
61 ; CHECK-NEXT: b.l.t (, %s10)
70 ; CHECK-NEXT: b.l.t (, %s10)
79 ; CHECK-NEXT: b.l.t (, %s10)
88 ; CHECK-NEXT: b.l.t (, %s10)
[all …]
H A Dctlz.ll18 ; CHECK-NEXT: b.l.t (, %s10)
27 ; CHECK-NEXT: b.l.t (, %s10)
37 ; CHECK-NEXT: b.l.t (, %s10)
47 ; CHECK-NEXT: b.l.t (, %s10)
57 ; CHECK-NEXT: b.l.t (, %s10)
67 ; CHECK-NEXT: b.l.t (, %s10)
77 ; CHECK-NEXT: b.l.t (, %s10)
87 ; CHECK-NEXT: b.l.t (, %s10)
97 ; CHECK-NEXT: b.l.t (, %s10)
106 ; CHECK-NEXT: b.l.t (, %s10)
[all …]
H A Dload.ll11 ; CHECK-NEXT: b.l.t (, %s10)
21 ; CHECK-NEXT: b.l.t (, %s10)
31 ; CHECK-NEXT: b.l.t (, %s10)
43 ; CHECK-NEXT: b.l.t (, %s10)
53 ; CHECK-NEXT: b.l.t (, %s10)
63 ; CHECK-NEXT: b.l.t (, %s10)
73 ; CHECK-NEXT: b.l.t (, %s10)
84 ; CHECK-NEXT: b.l.t (, %s10)
95 ; CHECK-NEXT: b.l.t (, %s10)
105 ; CHECK-NEXT: b.l.t (, %s10)
[all …]
H A Dnnd.ll7 ; CHECK-NEXT: b.l.t (, %s10)
17 ; CHECK-NEXT: b.l.t (, %s10)
28 ; CHECK-NEXT: b.l.t (, %s10)
39 ; CHECK-NEXT: b.l.t (, %s10)
49 ; CHECK-NEXT: b.l.t (, %s10)
59 ; CHECK-NEXT: b.l.t (, %s10)
69 ; CHECK-NEXT: b.l.t (, %s10)
79 ; CHECK-NEXT: b.l.t (, %s10)
89 ; CHECK-NEXT: b.l.t (, %s10)
99 ; CHECK-NEXT: b.l.t (, %s10)
[all …]
H A Dumax.ll32 ; CHECK-NEXT: b.l.t (, %s10)
43 ; CHECK-NEXT: b.l.t (, %s10)
54 ; CHECK-NEXT: b.l.t (, %s10)
66 ; CHECK-NEXT: b.l.t (, %s10)
78 ; CHECK-NEXT: b.l.t (, %s10)
98 ; CHECK-NEXT: b.l.t (, %s10)
107 ; CHECK-NEXT: b.l.t (, %s10)
115 ; CHECK-NEXT: b.l.t (, %s10)
123 ; CHECK-NEXT: b.l.t (, %s10)
131 ; CHECK-NEXT: b.l.t (, %s10)
[all …]
/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx10_vop3c.txt5 # W32: v_cmp_class_f32_e64 s10, -1, v2 ; encoding: [0x0a,0x00,0x88,0xd4,0xc1,0x04,0x02,0x00]
9 # W32: v_cmp_class_f32_e64 s10, -4.0, v2 ; encoding: [0x0a,0x00,0x88,0xd4,0xf7,0x04,0x02,0x00]
13 # W32: v_cmp_class_f32_e64 s10, -v1, v2 ; encoding: [0x0a,0x00,0x88,0xd4,0x01,0x05,0x02,0x20]
17 # W32: v_cmp_class_f32_e64 s10, 0, v2 ; encoding: [0x0a,0x00,0x88,0xd4,0x80,0x04,0x02,0x00]
21 # W32: v_cmp_class_f32_e64 s10, 0.5, v2 ; encoding: [0x0a,0x00,0x88,0xd4,0xf0,0x04,0x02,0x00]
25 # W32: v_cmp_class_f32_e64 s10, exec_hi, v2 ; encoding: [0x0a,0x00,0x88,0xd4,0x7f,0x04,0x02,0x00]
29 # W32: v_cmp_class_f32_e64 s10, exec_lo, v2 ; encoding: [0x0a,0x00,0x88,0xd4,0x7e,0x04,0x02,0x00]
33 # W32: v_cmp_class_f32_e64 s10, m0, v2 ; encoding: [0x0a,0x00,0x88,0xd4,0x7c,0x04,0x02,0x00]
37 # W32: v_cmp_class_f32_e64 s10, s1, v2 ; encoding: [0x0a,0x00,0x88,0xd4,0x01,0x04,0x02,0x00]
41 # W32: v_cmp_class_f32_e64 s10, s10
[all...]
H A Dgfx11_dasm_vop3_from_vopc.txt8 # W32-REAL16: v_cmp_class_f16_e64 s10, v1.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
9 # W32-FAKE16: v_cmp_class_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
14 # W32-REAL16: v_cmp_class_f16_e64 s10, v1.l, 0.5 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00]
15 # W32-FAKE16: v_cmp_class_f16_e64 s10, v1, 0.5 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0xe1,0x01,0x00]
20 # W32-REAL16: v_cmp_class_f16_e64 s10, v255.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00]
21 # W32-FAKE16: v_cmp_class_f16_e64 s10, v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00]
26 # W32-REAL16: v_cmp_class_f16_e64 s10, s1, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00]
27 # W32-FAKE16: v_cmp_class_f16_e64 s10, s1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00]
32 # W32-REAL16: v_cmp_class_f16_e64 s10, s105, v255.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00]
33 # W32-FAKE16: v_cmp_class_f16_e64 s10, s10
[all...]
H A Dgfx12_dasm_vop3c.txt8 # W32-REAL16: v_cmp_class_f16_e64 s10, v1.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
9 # W32-FAKE16: v_cmp_class_f16_e64 s10, v1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x05,0x02,0x00]
14 # W32-REAL16: v_cmp_class_f16_e64 s10, v255.l, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00]
15 # W32-FAKE16: v_cmp_class_f16_e64 s10, v255, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0xff,0x05,0x02,0x00]
20 # W32-REAL16: v_cmp_class_f16_e64 s10, s1, v2.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00]
21 # W32-FAKE16: v_cmp_class_f16_e64 s10, s1, v2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x01,0x04,0x02,0x00]
26 # W32-REAL16: v_cmp_class_f16_e64 s10, s105, v255.l ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00]
27 # W32-FAKE16: v_cmp_class_f16_e64 s10, s105, v255 ; encoding: [0x0a,0x00,0x7d,0xd4,0x69,0xfe,0x03,0x00]
32 # W32: v_cmp_class_f16_e64 s10, vcc_lo, s2 ; encoding: [0x0a,0x00,0x7d,0xd4,0x6a,0x04,0x00,0x00]
36 # W32: v_cmp_class_f16_e64 s10, vcc_h
[all...]
/llvm-project/llvm/test/MC/VE/
H A DLD.s18 # CHECK-INST: ld %s11, 20(%s10, %s11)
20 ld %s11, 20(%s10, %s11)
22 # CHECK-INST: ldu %s11, 20(%s10, %s11)
24 ldu %s11, 20(%s10, %s11)
26 # CHECK-INST: ldl.sx %s11, 20(%s10, %s11)
28 ldl.sx %s11, 20(%s10, %s11)
30 # CHECK-INST: ldl.zx %s11, 20(%s10, %s11)
32 ldl.zx %s11, 20(%s10, %s11)
34 # CHECK-INST: ld2b.sx %s11, 20(%s10, %s11)
36 ld2b.sx %s11, 20(%s10, %s11)
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dfmin3.ll13 ; SI-NEXT: s_mov_b32 s10, -1
14 ; SI-NEXT: s_mov_b32 s14, s10
16 ; SI-NEXT: s_mov_b32 s18, s10
18 ; SI-NEXT: s_mov_b32 s22, s10
43 ; VI-NEXT: s_mov_b32 s10, -1
44 ; VI-NEXT: s_mov_b32 s14, s10
51 ; VI-NEXT: s_mov_b32 s18, s10
55 ; VI-NEXT: s_mov_b32 s6, s10
77 ; GFX9-NEXT: s_mov_b32 s4, s10
102 ; GFX11-NEXT: s_mov_b32 s10,
[all...]
H A Dfmax3.ll13 ; SI-NEXT: s_mov_b32 s10, -1
14 ; SI-NEXT: s_mov_b32 s14, s10
16 ; SI-NEXT: s_mov_b32 s18, s10
18 ; SI-NEXT: s_mov_b32 s22, s10
43 ; VI-NEXT: s_mov_b32 s10, -1
44 ; VI-NEXT: s_mov_b32 s14, s10
51 ; VI-NEXT: s_mov_b32 s18, s10
55 ; VI-NEXT: s_mov_b32 s6, s10
77 ; GFX9-NEXT: s_mov_b32 s4, s10
102 ; GFX11-NEXT: s_mov_b32 s10,
[all...]
H A Dllvm.fmuladd.f16.ll19 ; SI-NEXT: s_mov_b32 s10, -1
20 ; SI-NEXT: s_mov_b32 s14, s10
27 ; SI-NEXT: s_mov_b32 s18, s10
31 ; SI-NEXT: s_mov_b32 s6, s10
53 ; VI-FLUSH-NEXT: s_mov_b32 s10, -1
54 ; VI-FLUSH-NEXT: s_mov_b32 s14, s10
61 ; VI-FLUSH-NEXT: s_mov_b32 s18, s10
65 ; VI-FLUSH-NEXT: s_mov_b32 s6, s10
81 ; VI-DENORM-NEXT: s_mov_b32 s10, -1
82 ; VI-DENORM-NEXT: s_mov_b32 s14, s10
[all...]
/llvm-project/llvm/test/MC/RISCV/
H A Drv32zdinx-valid.s
/llvm-project/llvm/test/MC/AArch64/
H A Dneon-scalar-fp-compare.s10 fcmeq s10, s11, s12
14 // CHECK: fcmeq s10, s11, s12 // encoding: [0x6a,0xe5,0x2c,0x5e]
22 fcmeq s10, s11, #0.0
25 fcmeq s10, s11, #0
29 // CHECK: fcmeq s10, s11, #0.0 // encoding: [0x6a,0xd9,0xa0,0x5e]
32 // CHECK: fcmeq s10, s11, #0.0 // encoding: [0x6a,0xd9,0xa0,0x5e]
40 fcmge s10, s11, s12
44 // CHECK: fcmge s10, s11, s12 // encoding: [0x6a,0xe5,0x2c,0x7e]
52 fcmge s10, s11, #0.0
55 fcmge s10, s11, #0
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dllvm.amdgcn.image.gather4.dim.ll19 ; GFX6-NEXT: s_mov_b32 s8, s10
21 ; GFX6-NEXT: s_mov_b32 s10, s12
42 ; GFX10NSA-NEXT: s_mov_b32 s8, s10
44 ; GFX10NSA-NEXT: s_mov_b32 s10, s12
63 ; GFX12-NEXT: s_mov_b32 s8, s10
65 ; GFX12-NEXT: s_mov_b32 s10, s12
87 ; GFX6-NEXT: s_mov_b32 s8, s10
89 ; GFX6-NEXT: s_mov_b32 s10, s12
119 ; GFX10NSA-NEXT: s_mov_b32 s8, s10
121 ; GFX10NSA-NEXT: s_mov_b32 s10, s12
[all …]
/llvm-project/llvm/test/MC/ARM/
H A Dvpush-vpop.s7 vpush {s8, s9, s10, s11, s12}
9 vpop {s8, s9, s10, s11, s12}
12 vpush.16 {s8, s9, s10, s11, s12}
14 vpop.64 {s8, s9, s10, s11, s12}
17 @ CHECK-THUMB: vpush {s8, s9, s10, s11, s12} @ encoding: [0x2d,0xed,0x05,0x4a]
19 @ CHECK-THUMB: vpop {s8, s9, s10, s11, s12} @ encoding: [0xbd,0xec,0x05,0x4a]
22 @ CHECK-ARM: vpush {s8, s9, s10, s11, s12} @ encoding: [0x05,0x4a,0x2d,0xed]
24 @ CHECK-ARM: vpop {s8, s9, s10, s11, s12} @ encoding: [0x05,0x4a,0xbd,0xec]
27 @ CHECK-THUMB: vpush {s8, s9, s10, s11, s12} @ encoding: [0x2d,0xed,0x05,0x4a]
29 @ CHECK-THUMB: vpop {s8, s9, s10, s11, s12} @ encoding: [0xbd,0xec,0x05,0x4a]
[all …]

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