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/llvm-project/llvm/test/MC/ARM/
H A Ddirective-arch_extension-fp.s22 vselgt.f32 s0, s0, s0
24 vselge.f32 s0, s0, s0
26 vseleq.f32 s0, s0, s0
28 vselvs.f32 s0, s0, s0
30 vmaxnm.f32 s0, s0, s0
32 vminnm.f32 s0, s0, s0
48 vcvtb.f64.f16 d0, s0
50 vcvtb.f16.f64 s0, d0
52 vcvtt.f64.f16 d0, s0
54 vcvtt.f16.f64 s0, d0
[all …]
H A Ddirective-arch_extension-simd.s19 vmaxnm.f32 s0, s0, s0
21 vminnm.f32 s0, s0, s0
29 vcvta.s32.f32 s0, s0
31 vcvta.u32.f32 s0, s0
33 vcvta.s32.f64 s0, d0
35 vcvta.u32.f64 s0, d0
37 vcvtn.s32.f32 s0, s0
39 vcvtn.u32.f32 s0, s0
41 vcvtn.s32.f64 s0, d0
43 vcvtn.u32.f64 s0, d0
[all …]
H A Dfullfp16.s6 vadd.f16 s0, s1, s0
7 @ ARM: vadd.f16 s0, s1, s0 @ encoding: [0x80,0x09,0x30,0xee]
8 @ THUMB: vadd.f16 s0, s1, s0 @ encoding: [0x30,0xee,0x80,0x09]
10 vsub.f16 s0, s1, s0
11 @ ARM: vsub.f16 s0, s1, s0 @ encoding: [0xc0,0x09,0x30,0xee]
12 @ THUMB: vsub.f16 s0, s1, s0 @ encoding: [0x30,0xee,0xc0,0x09]
14 vdiv.f16 s0, s1, s0
15 @ ARM: vdiv.f16 s0, s1, s0 @ encoding: [0x80,0x09,0x80,0xee]
16 @ THUMB: vdiv.f16 s0, s1, s0 @ encoding: [0x80,0xee,0x80,0x09]
18 vmul.f16 s0, s1, s0
[all …]
/llvm-project/llvm/test/Transforms/GlobalOpt/
H A Dcrash-2.ll6 %struct.S0.1.7.13 = type { i8, i8, i8, i8, i16, [2 x i8] }
11 @g_71 = internal global %struct.S0.1.7.13 { i8 1, i8 -93, i8 58, i8 -1, i16 -5, [2 x i8] undef }, a…
14 …S0.1.7.13, %struct.S0.1.7.13* @g_71, i32 0, i32 0), i8* getelementptr inbounds (%struct.S0.1.7.13,…
/llvm-project/llvm/test/CodeGen/Thumb2/
H A Dmve-vecreduce-fminmax.ll8 ; CHECK-NEXT: vminnm.f32 s0, s0, s1
19 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1
20 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2
25 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s1
26 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s
[all...]
H A Dmve-vecreduce-fmul.ll8 ; CHECK-NEXT: vmul.f32 s0, s0, s1
9 ; CHECK-NEXT: vmul.f32 s0, s4, s0
20 ; CHECK-FP-NEXT: vmul.f32 s0, s0, s1
21 ; CHECK-FP-NEXT: vmul.f32 s0, s0, s2
22 ; CHECK-FP-NEXT: vmul.f32 s0, s4, s0
27 ; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s1
28 ; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s2
29 ; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s3
30 ; CHECK-NOFP-NEXT: vmul.f32 s0, s4, s0
42 ; CHECK-FP-NEXT: vmul.f32 s0, s0, s1
[all …]
H A Dmve-vecreduce-fadd.ll8 ; CHECK-NEXT: vadd.f32 s0, s0, s1
9 ; CHECK-NEXT: vadd.f32 s0, s4, s0
20 ; CHECK-FP-NEXT: vadd.f32 s0, s0, s1
21 ; CHECK-FP-NEXT: vadd.f32 s0, s0, s2
22 ; CHECK-FP-NEXT: vadd.f32 s0, s4, s0
27 ; CHECK-NOFP-NEXT: vadd.f32 s0, s0, s1
28 ; CHECK-NOFP-NEXT: vadd.f32 s0, s0, s2
29 ; CHECK-NOFP-NEXT: vadd.f32 s0, s0, s3
30 ; CHECK-NOFP-NEXT: vadd.f32 s0, s4, s0
42 ; CHECK-FP-NEXT: vadd.f32 s0, s0, s1
[all …]
/llvm-project/llvm/test/MC/RISCV/
H A Dcompress-rv32i.s30 # CHECK-ALIAS: addi s0, sp, 1020
31 # CHECK-INST: c.addi4spn s0, sp, 1020
33 addi s0, sp, 1020
36 # CHECK-ALIAS: lw s0, 124(a5)
37 # CHECK-INST: c.lw s0, 124(a5)
39 lw s0, 124(a5)
42 # CHECK-ALIAS: sw s0, 124(a5)
43 # CHECK-INST: c.sw s0, 124(a5)
45 sw s0, 124(a5)
78 # CHECK-ALIAS: srli s0, s
[all...]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dsve-streaming-mode-fixed-length-fp-rounding.ll26 ; NONEON-NOSVE-NEXT: fcvt s0, h0
27 ; NONEON-NOSVE-NEXT: frintp s0, s0
28 ; NONEON-NOSVE-NEXT: fcvt h0, s0
31 ; NONEON-NOSVE-NEXT: fcvt s0, h0
32 ; NONEON-NOSVE-NEXT: frintp s0, s0
33 ; NONEON-NOSVE-NEXT: fcvt h0, s0
36 ; NONEON-NOSVE-NEXT: fcvt s0, h0
37 ; NONEON-NOSVE-NEXT: frintp s0, s0
38 ; NONEON-NOSVE-NEXT: fcvt h0, s0
41 ; NONEON-NOSVE-NEXT: fcvt s0, h0
[all …]
H A Dsve-streaming-mode-fixed-length-fp-arith.ll29 ; NONEON-NOSVE-NEXT: fcvt s0, h0
31 ; NONEON-NOSVE-NEXT: fadd s0, s1, s0
34 ; NONEON-NOSVE-NEXT: fcvt h0, s0
37 ; NONEON-NOSVE-NEXT: fcvt s0, h0
38 ; NONEON-NOSVE-NEXT: fadd s0, s1, s0
41 ; NONEON-NOSVE-NEXT: fcvt h0, s0
44 ; NONEON-NOSVE-NEXT: fcvt s0, h0
45 ; NONEON-NOSVE-NEXT: fadd s0, s1, s0
48 ; NONEON-NOSVE-NEXT: fcvt h0, s0
51 ; NONEON-NOSVE-NEXT: fcvt s0, h0
[all …]
/llvm-project/llvm/test/CodeGen/VE/Vector/
H A Dvec_broadcast.ll9 ; CHECK-NEXT: vbrd %v0, %s0
19 ; CHECK-NEXT: lea %s0, 256
20 ; CHECK-NEXT: lvl %s0
33 ; CHECK-NEXT: vbrd %v0, %s0
43 ; CHECK-NEXT: lea %s0, 256
44 ; CHECK-NEXT: lvl %s0
55 ; CHECK-NEXT: and %s0, %s0, (32)0
58 ; CHECK-NEXT: vbrd %v0, %s0
68 ; CHECK-NEXT: lea %s0, 256
69 ; CHECK-NEXT: lvl %s0
[all …]
/llvm-project/llvm/test/CodeGen/VE/Scalar/
H A Dbr_jt.ll14 ; CHECK-NEXT: and %s0, %s0, (32)0
15 ; CHECK-NEXT: breq.w 1, %s0, .LBB0_1
17 ; CHECK-NEXT: breq.w 4, %s0, .LBB0_5
19 ; CHECK-NEXT: brne.w 2, %s0, .LBB0_6
21 ; CHECK-NEXT: or %s0, 0, (0)1
22 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
25 ; CHECK-NEXT: or %s0, 7, (0)1
27 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
30 ; CHECK-NEXT: or %s0, 3, (0)1
31 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
[all …]
H A Dselect_cc.ll12 ; CHECK-NEXT: xor %s0, %s0, %s1
13 ; CHECK-NEXT: cmov.w.ne %s2, %s3, %s0
14 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
25 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
26 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
27 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
38 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
39 ; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
40 ; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
51 ; CHECK-NEXT: cmpu.w %s0, %s0, %s1
[all …]
H A Dctlz.ll14 ; CHECK-NEXT: ldz %s0, %s0
15 ; CHECK-NEXT: lea %s0, 64(, %s0)
16 ; CHECK-NEXT: cmov.l.ne %s0, %s2, %s1
26 ; CHECK-NEXT: ldz %s0, %s0
35 ; CHECK-NEXT: sll %s0, %s0, 32
36 ; CHECK-NEXT: ldz %s0, %s0
45 ; CHECK-NEXT: sll %s0, %s0, 32
46 ; CHECK-NEXT: ldz %s0, %s0
55 ; CHECK-NEXT: sll %s0, %s0, 48
56 ; CHECK-NEXT: ldz %s0, %s0
[all …]
H A Daddition.ll6 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
7 ; CHECK-NEXT: sll %s0, %s0, 56
8 ; CHECK-NEXT: sra.l %s0, %s0, 56
17 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
18 ; CHECK-NEXT: sll %s0, %s0, 48
19 ; CHECK-NEXT: sra.l %s0, %s0, 48
28 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
29 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
38 ; CHECK-NEXT: adds.l %s0, %s1, %s0
48 ; CHECK-NEXT: adds.l %s0, %s2, %s0
[all …]
H A Dsubtraction.ll6 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
7 ; CHECK-NEXT: sll %s0, %s0, 56
8 ; CHECK-NEXT: sra.l %s0, %s0, 56
17 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
18 ; CHECK-NEXT: sll %s0, %s0, 48
19 ; CHECK-NEXT: sra.l %s0, %s0, 48
28 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
29 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
38 ; CHECK-NEXT: subs.l %s0, %s0, %s1
48 ; CHECK-NEXT: cmpu.l %s3, %s0, %s2
[all …]
H A Dload_off.ll16 ; CHECK-NEXT: lea %s0, bufi8@lo
17 ; CHECK-NEXT: and %s0, %s0, (32)0
18 ; CHECK-NEXT: lea.sl %s0, bufi8@hi(, %s0)
19 ; CHECK-NEXT: ld1b.sx %s0, 2(, %s0)
30 ; CHECK-NEXT: lea %s0, bufi16@lo
31 ; CHECK-NEXT: and %s0, %s0, (32)0
32 ; CHECK-NEXT: lea.sl %s0, bufi16@hi(, %s0)
33 ; CHECK-NEXT: ld2b.sx %s0, 4(, %s0)
44 ; CHECK-NEXT: lea %s0, bufi32@lo
45 ; CHECK-NEXT: and %s0, %s0, (32)0
[all …]
H A Datomic.ll16 ; CHECK-NEXT: lea %s0, c@lo
17 ; CHECK-NEXT: and %s0, %s0, (32)0
18 ; CHECK-NEXT: lea.sl %s0, c@hi(, %s0)
19 ; CHECK-NEXT: and %s0, -4, %s0
20 ; CHECK-NEXT: ldl.sx %s2, (, %s0)
30 ; CHECK-NEXT: cas.w %s2, (%s0), %s3
33 ; CHECK-NEXT: sll %s0, %s2, 56
34 ; CHECK-NEXT: sra.l %s0, %s0, 56
47 ; CHECK-NEXT: lea %s0, s@lo
48 ; CHECK-NEXT: and %s0, %s0, (32)0
[all …]
H A Dmultiply.ll6 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
7 ; CHECK-NEXT: sll %s0, %s0, 56
8 ; CHECK-NEXT: sra.l %s0, %s0, 56
17 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
18 ; CHECK-NEXT: sll %s0, %s0, 48
19 ; CHECK-NEXT: sra.l %s0, %s0, 48
28 ; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
29 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
38 ; CHECK-NEXT: muls.l %s0, %s1, %s0
48 ; CHECK-NEXT: or %s5, 0, %s0
[all …]
/llvm-project/llvm/test/CodeGen/ARM/
H A Dinlineasm-fp-half.ll40 ; NO-FP16-SOFTFP-NEXT: vmov s0, r0
42 ; NO-FP16-SOFTFP-NEXT: vmov.f32 s0, s0
44 ; NO-FP16-SOFTFP-NEXT: vmov r0, s0
50 ; NO-FP16-HARD-NEXT: vmov.f32 s0, s0
56 ; FP16-SOFTFP-NEXT: vmov.f16 s0, r0
57 ; FP16-SOFTFP-NEXT: vmov.f16 r0, s0
58 ; FP16-SOFTFP-NEXT: vmov s0, r0
60 ; FP16-SOFTFP-NEXT: vmov.f32 s0, s0
62 ; FP16-SOFTFP-NEXT: vmov r0, s0
67 ; FP16-HARD-NEXT: vmov.f16 r0, s0
[all …]
H A Dfp16-fullfp16.ll6 ; CHECK: vldr.16 s0, [r1]
8 ; CHECK-NEXT: vadd.f16 s0, s2, s0
9 ; CHECK-NEXT: vstr.16 s0, [r0]
20 ; CHECK: vldr.16 s0, [r1]
22 ; CHECK-NEXT: vsub.f16 s0, s2, s0
23 ; CHECK-NEXT: vstr.16 s0, [r0]
34 ; CHECK: vldr.16 s0, [r1]
36 ; CHECK-NEXT: vmul.f16 s0, s2, s0
37 ; CHECK-NEXT: vstr.16 s0, [r0]
48 ; CHECK: vldr.16 s0, [r1]
[all …]
H A Dfp16-vminmaxnm-safe.ll8 ; CHECK-NEXT: vmov.f16 s0, r0
10 ; CHECK-NEXT: vcmp.f16 s2, s0
12 ; CHECK-NEXT: vselgt.f16 s0, s0, s2
13 ; CHECK-NEXT: vmov r0, s0
24 ; CHECK-NEXT: vmov.f16 s0, r1
26 ; CHECK-NEXT: vcmp.f16 s2, s0
28 ; CHECK-NEXT: vselgt.f16 s0, s2, s0
29 ; CHECK-NEXT: vmov r0, s0
[all...]
H A Dfast-isel-conversion.ll10 ; ARM: vmov s0, r0
11 ; ARM: vcvt.f32.s32 s0, s0
13 ; THUMB: vmov s0, r0
14 ; THUMB: vcvt.f32.s32 s0, s0
25 ; ARM: vmov s0, r0
26 ; ARM: vcvt.f32.s32 s0, s0
29 ; THUMB: vmov s0, r0
30 ; THUMB: vcvt.f32.s32 s0, s0
41 ; ARM: vmov s0, r0
42 ; ARM: vcvt.f32.s32 s0, s0
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dsub.v2i16.ll238 ; GFX9-NEXT: s_lshr_b32 s1, s0, 16
239 ; GFX9-NEXT: s_sub_i32 s0, s0, 0xffc0ffc0
241 ; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1
246 ; GFX8-NEXT: s_lshr_b32 s1, s0, 16
247 ; GFX8-NEXT: s_and_b32 s0, s0, 0xffff
248 ; GFX8-NEXT: s_add_i32 s0, s0,
[all...]
/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dcombine-commute-int-const-lhs.mir8 liveins: $s0
11 ; CHECK: liveins: $s0
13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
16 ; CHECK-NEXT: $s0 = COPY %add(s32)
18 %0:_(s32) = COPY $s0
21 $s0 = COPY %add
30 liveins: $s0
33 ; CHECK: liveins: $s0
35 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
38 ; CHECK-NEXT: $s0 = COPY %mul(s32)
[all …]

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