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/freebsd-src/sys/contrib/alpine-hal/
H A Dal_hal_udma_regs_gen.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
100 /* [0x0] Target-ID control */
102 /* [0x4] TX queue 0/1 Target-ID */
104 /* [0x8] TX queue 2/3 Target-ID */
106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
112 /* [0x0] TX queue 0/1 Target-Address */
114 /* [0x4] TX queue 2/3 Target-Address */
116 /* [0x8] RX queue 0/1 Target-Address */
118 /* [0xc] RX queue 2/3 Target-Address */
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/freebsd-src/sys/contrib/device-tree/Bindings/usb/
H A Dqcom,pmic-typec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,pmic-type
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/freebsd-src/sys/contrib/device-tree/Bindings/serial/
H A Dst,stm32-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uar
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H A Dserial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd-src/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_ec_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
86 /* [0x0] Rx FIFO input controller configuration 1 */
88 /* [0x4] Rx FIFO input controller configuration 2 */
90 /* [0x8] Threshold to start reading packet from the Rx FIFO */
92 /* [0xc] Threshold to stop writing packet to the Rx FIFO */
96 /* [0x14] Rx FIFO input controller loopback FIFO configuratio ... */
214 /* [0x38] VLAN p-bits table address */
216 /* [0x3c] VLAN p-bits table data */
374 /* [0x0] Tx FIFO Wr configuration */
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H A Dal_hal_eth_mac_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
307 struct al_eth_mac_10g_stats_v3_rx rx; member
309 struct al_eth_mac_10g_stats_v3_tx tx; member
428 /* [0x5c] SerDes TX FIFO control */
430 /* [0x60] SerDes TX FIFO status */
550 /* [0x4] TX ASYNC FIFO configuration */
552 /* [0x8] TX ASYNC FIFO configuration */
554 /* [0xc] TX ASYNC FIFO configuration */
556 /* [0x10] TX ASYNC FIFO configuration */
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/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Floria
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H A Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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/freebsd-src/sys/contrib/device-tree/Bindings/mtd/
H A Dgpmi-nand.txt1 * Freescale General-Purpose Media Interface (GPMI)
7 - compatible : should be "fsl,<chip>-gpmi-nand", chip can be:
13 - reg : should contain registers location and length for gpmi and bch.
14 - reg-names: Should contain the reg names "gpmi-nand" and "bch"
15 - interrupts : BCH interrupt number.
16 - interrupt-names : Should be "bch".
17 - dmas: DMA specifier, consisting of a phandle to DMA controller node
19 Refer to dma.txt and fsl-mxs-dma.txt for details.
20 - dma-names: Must be "rx-tx".
21 - clocks : clocks phandle and clock specifier corresponding to each clock
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H A Dgpmi-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/gpmi-nan
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/freebsd-src/share/man/man4/
H A Dbce.41 .\" Copyright (c) 2006-2014 QLogic Corporation
35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
62 .Bl -item -offset indent -compact
72 10/100/1000Mbps operation in full-duplex mode
74 10/100Mbps operation in half-duplex mode
80 .Bl -tag -width ".Cm 10baseT/UTP"
92 .Cm full-duplex
94 .Cm half-duplex
102 .Cm full-duplex
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/freebsd-src/sys/dev/mwl/
H A Dif_mwlvar.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
47 #define MWL_TXBUF 256 /* number of TX descriptors/buffers */
50 #define MWL_TXACKBUF (MWL_TXBUF/2) /* number of TX ACK desc's/buffers */
53 #define MWL_RXDESC 256 /* number of RX descriptors */
56 #define MWL_RXBUF ((5*MWL_RXDESC)/2)/* number of RX dma buffers */
63 #define MWL_TXDESC 6 /* max tx descriptors/segments */
65 #define MWL_TXDESC 1 /* max tx descriptors/segments */
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/freebsd-src/sys/contrib/device-tree/src/arm64/qcom/
H A Dpm8150b.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/iio/qcom,spmi-vadc.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-binding
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/freebsd-src/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_regs.h22 Boston, MA 02110-1301, USA.
32 /* N-PHY registers. */
36 #define BWN_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
38 #define BWN_NPHY_TXERR BWN_PHY_N(0x007) /* TX error */
41 #define BWN_NPHY_4WI_ADDR BWN_PHY_N(0x00B) /* Four-wire bus address */
42 #define BWN_NPHY_4WI_DATAHI BWN_PHY_N(0x00C) /* Four-wire bus data high */
43 #define BWN_NPHY_4WI_DATALO BWN_PHY_N(0x00D) /* Four-wire bus data low */
44 #define BWN_NPHY_BIST_STAT0 BWN_PHY_N(0x00E) /* Built-in self test status 0 */
45 #define BWN_NPHY_BIST_STAT1 BWN_PHY_N(0x00F) /* Built-in self test status 1 */
80 #define BWN_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */
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/freebsd-src/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_port.h2 * Copyright 2008-2013 Freescale Semiconductor Inc.
150 /** @Description BMI Rx port register map */
152 uint32_t fmbm_rcfg; /**< Rx Configuration */
153 uint32_t fmbm_rst; /**< Rx Status */
154 uint32_t fmbm_rda; /**< Rx DMA attributes*/
155 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
156 uint32_t fmbm_rfed; /**< Rx Frame End Data*/
157 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
158 uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
159 uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
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/freebsd-src/sys/contrib/device-tree/src/arm64/broadcom/northstar2/
H A Dns2-svk.dts33 /dts-v1/;
39 compatible = "brcm,ns2-svk", "brcm,ns2";
49 stdout-path = "serial0:115200n8";
113 spi-max-frequency = <5000000>;
114 spi-cpha;
115 spi-cpol;
117 pl022,slave-tx-disabl
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/freebsd-src/crypto/openssl/crypto/aes/asm/
H A Daesni-sha1-x86_64.pl2 # Copyright 2011-2020 The OpenSSL Project Authors. All Rights Reserved.
19 # This is AESNI-CBC+SHA1 "stitch" implementation. The idea, as spelled
21 # that since AESNI-CBC encrypt exhibit *very* low instruction-level
24 # SHA1 instruction sequences(*) are taken from sha1-x86_64.pl and
26 # cycles per processed byte, less is better, for standalone AESNI-CBC
30 # AES-128-CBC +SHA1 stitch gain
40 # AES-192-CBC
47 # AES-256-CBC
57 # (*) There are two code paths: SSSE3 and AVX. See sha1-568.pl for
59 # results collected on AVX-capable CPU, i.e. apply on OSes that
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/freebsd-src/sys/dev/mii/
H A Dbrgphyreg.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
113 #define BRGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
114 #define BRGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
115 #define BRGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
116 #define BRGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
119 #define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */
121 #define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* TX output disabled */
124 #define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */
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/freebsd-src/sys/contrib/dev/athk/ath12k/
H A Dce.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
12 /* Byte swap data words */
21 /* Threshold to poll for tx completion in case of Interrupt disabled CE's */
29 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
31 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
36 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
37 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
83 /* #entries in source ring - Must be a power of 2 */
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/freebsd-src/sys/contrib/dev/athk/ath11k/
H A Dce.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
11 /* Byte swap data words */
24 /* Threshold to poll for tx completion in case of Interrupt disabled CE's */
35 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
37 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
42 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
43 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
107 /* #entries in source ring - Must be a power of 2 */
116 /* #entries in destination ring - Must be a power of 2 */
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/freebsd-src/sys/contrib/ena-com/ena_defs/
H A Dena_admin_defs.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2015-2023 Amazon.com, Inc. or its affiliates.
45 /* customer metrics - in correlation with
192 /* Bypass Rx UDP ordering */
206 * 1 : ctrl_data - control buffer address valid
207 * 2 : ctrl_data_indirect - contro
829 uint32_t tx; global() member
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/freebsd-src/sys/dev/le/
H A Dlancereg.h3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
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/freebsd-src/crypto/openssl/crypto/sha/asm/
H A Dsha1-x86_64.pl2 # Copyright 2006-2020 The OpenSSL Project Authors. All Rights Reserved.
19 # It was brought to my attention that on EM64T compiler-generated code
20 # was far behind 32-bit assembler implementation. This is unlike on
21 # Opteron where compiler-generated code was only 15% behind 32-bit
23 # There was suggestion to mechanically translate 32-bit code, but I
25 # capacity to fully utilize SHA-1 parallelism. Therefore this fresh
26 # implementation:-) However! While 64-bit code does perform better
27 # on Opteron, I failed to beat 32-bit assembler on EM64T core. Well,
28 # x86_64 does offer larger *addressable* bank, but out-of-order core
30 # core must have managed to run-time optimize even 32-bit code just as
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/freebsd-src/sys/dev/netmap/
H A Dnetmap_bdg.c2 * Copyright (C) 2013-2016 Universita` di Pisa
31 --- VALE SWITCH ---
44 On the rx ring, the per-port lock is grabbed initially to reserve
48 (A similar thing is done on the tx ring for NIC and host stack
54 * OS-specific code that is used only within this file.
55 * Other OS-specific code that must be accessed by drivers
114 struct nm_bridge *b = vp->na_bdg; in netmap_bdg_name()
117 return b->bdg_basename; in netmap_bdg_name()
145 int colon_pos = -1; in nm_bdg_name_validate()
149 return -1; in nm_bdg_name_validate()
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/freebsd-src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/net/ti-dp83867.h>
11 model = "PHYTEC phyCORE-i.MX8MP";
12 compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
24 reg_vdd_io: regulator-vdd-i
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