| /freebsd-src/sys/contrib/device-tree/Bindings/sound/ |
| H A D | qcom,wcd938x-sdw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd938x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC.
14 It has RX and TX Soundwire slave devices. This bindings is for the
24 qcom,tx-port-mapping:
26 Specifies static port mapping between slave and master tx ports.
27 In the order of slave port index.
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| H A D | rockchip,i2s-tdm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
18 - $ref: dai-common.yaml#
23 - rockchip,px30-i2s-tdm
24 - rockchip,rk1808-i2s-tdm
25 - rockchip,rk3308-i2s-tdm
26 - rockchip,rk3568-i2s-tdm
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| H A D | qcom,wcd938x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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| /freebsd-src/sys/contrib/device-tree/Bindings/hsi/ |
| H A D | omap-ssi.txt | 9 - compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi"
10 - reg-names: Contains the values "sys" and "gdd" (in this order).
11 - reg: Contains a matching register specifier for each entry
12 in reg-names.
13 - interrupt-names: Contains the value "gdd_mpu".
14 - interrupts: Contains matching interrupt information for each entry
15 in interrupt-names.
16 - ranges: Represents the bus address mapping between the main
18 - clock-names: Must include the following entries:
22 - clocks: Contains a matching clock specifier for each entry in
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| /freebsd-src/sys/contrib/device-tree/Bindings/net/ |
| H A D | ibm,emac.txt | 8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
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| H A D | cavium-pip.txt | 10 - compatible: "cavium,octeon-3860-pip"
14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
18 - #size-cells: Must be <0>.
21 - compatible: "cavium,octeon-3860-pip-interface"
25 - reg: The interface number.
27 - #address-cells: Must be <1>.
29 - #size-cells: Must be <0>.
31 Properties for PIP port which is a child the PIP interface:
32 - compatible: "cavium,octeon-3860-pip-port"
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| /freebsd-src/sys/contrib/xen/io/ |
| H A D | netif.h | 4 * Unified network-device I/O interface for Xen guest OSes.
24 * Copyright (c) 2003-2004, Keir Fraser
54 * If the client sends notification for rx requests then it should specify
55 * feature 'feature-rx-notify' via xenbus. Otherwise the backend will assume
60 * "feature-split-event-channels" is introduced to separate guest TX
61 * and RX notification. Backend either doesn't support this feature or
65 * channels for TX and RX, advertise them to backend as
66 * "event-channel-tx" and "event-channel-rx" respectively. If frontend
67 * doesn't want to use this feature, it just writes "event-channel"
73 * If supported, the backend will write the key "multi-queue-max-queues" to
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| /freebsd-src/sys/contrib/device-tree/Bindings/iommu/ |
| H A D | mediatek,iommu.txt | 5 pagetable, and only supports 4K size page mapping. Generation two uses the
6 ARM Short-Descriptor translation table format for address translation.
14 +--------+
16 gals0-rx gals1-rx (Global Async Local Sync rx)
19 gals0-tx gals1-tx (Global Async Local Sync tx)
21 +--------+
25 +----------------+-------
27 | gals-rx There may be GALS in some larbs.
30 | gals-tx
36 +-----+-----+ +----+----+
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| H A D | mediatek,iommu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
15 pagetable, and only supports 4K size page mapping. Generation two uses the
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
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| /freebsd-src/sys/contrib/device-tree/Bindings/ata/ |
| H A D | qcom-sata.txt | 3 SATA nodes are defined to describe on-chip Serial ATA controllers.
7 - compatible : compatible list, must contain "generic-ahci"
8 - interrupts : <interrupt mapping for SATA IRQ>
9 - reg : <registers mapping>
10 - phys : Must contain exactly one entry as specified
11 in phy-bindings.txt
12 - phy-names : Must be "sata-phy"
14 Required properties for "qcom,ipq806x-ahci" compatible:
15 - clocks : Must contain an entry for each entry in clock-names.
16 - clock-names : Shall be:
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| /freebsd-src/sys/contrib/ncsw/inc/flib/ |
| H A D | fsl_fman_port.h | 2 * Copyright 2008-2013 Freescale Semiconductor Inc.
137 /** @Description General port defines */
148 /** @Collection FM Port Register Map */
150 /** @Description BMI Rx port register map */
152 uint32_t fmbm_rcfg; /**< Rx Configuration */
153 uint32_t fmbm_rst; /**< Rx Status */
154 uint32_t fmbm_rda; /**< Rx DMA attributes*/
155 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
156 uint32_t fmbm_rfed; /**< Rx Frame End Data*/
157 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
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| /freebsd-src/sys/contrib/device-tree/Bindings/net/dsa/ |
| H A D | qca8k.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
14 describing a port needs to have a valid phandle referencing the internal PHY
15 it is connected to. This is because there is no N:N mapping of port and PHY
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17 the switch node and declare the phandle for the port, referencing the internal
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
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| /freebsd-src/sys/contrib/device-tree/Bindings/media/ |
| H A D | imx7-mipi-csi2.txt | 5 --------------
7 This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
8 compatible with previous version of Samsung D-phy.
12 - compatible : "fsl,imx7-mipi-csi2";
13 - reg : base address and length of the register set for the device;
14 - interrupts : should contain MIPI CSIS interrupt;
15 - clocks : list of clock specifiers, see
16 Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
17 - clock-names : must contain "pclk", "wrap" and "phy" entries, matching
19 - power-domains : a phandle to the power domain, see
[all …]
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| H A D | samsung-mipi-csis.txt | 1 Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS)
2 -------------------------------------------------------------
6 - compatible : "samsung,s5pv210-csis" for S5PV210 (S5PC110),
7 "samsung,exynos4210-csis" for Exynos4210 (S5PC210),
8 "samsung,exynos4212-csis" for Exynos4212/Exynos4412,
9 "samsung,exynos5250-csis" for Exynos5250;
10 - reg : offset and length of the register set for the device;
11 - interrupts : should contain MIPI CSIS interrupt; the format of the
13 - bus-width : maximum number of data lanes supported (SoC specific);
14 - vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V);
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| /freebsd-src/sys/dev/sfxge/common/ |
| H A D | ef10_nic.c | 1 /*-
2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
52 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || in efx_mcdi_get_port_assignment()
53 enp->en_family == EFX_FAMILY_MEDFORD || in efx_mcdi_get_port_assignment()
54 enp->en_family == EFX_FAMILY_MEDFORD2); in efx_mcdi_get_port_assignment()
98 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || in efx_mcdi_get_port_modes()
99 enp->en_family == EFX_FAMILY_MEDFORD || in efx_mcdi_get_port_modes()
100 enp->en_family == EFX_FAMILY_MEDFORD2); in efx_mcdi_get_port_modes()
161 efx_port_t *epp = &(enp->en_port); in ef10_nic_get_port_mode_bandwidth()
171 /* No port mode info available. */ in ef10_nic_get_port_mode_bandwidth()
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| H A D | efx_regs_mcdi.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved.
32 /* Power-on reset state */
54 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
57 /* The rest of these are firmware-defined */
65 /* Values to be written to the per-port status dword in shared
94 * | | \--- Response
95 * | \------- Error
96 * \------------------------------ Resync (always set)
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| /freebsd-src/sys/arm/ti/cpsw/ |
| H A D | if_cpsw.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
36 * and in the TMS320C6452 3 Port Switch Ethernet Subsystem TRM.
38 * It is basically a single Ethernet port (port 0) wired internally to
39 * a 3-port stor
734 cpsw_get_fdt_data(struct cpsw_softc * sc,int port) cpsw_get_fdt_data() argument
1605 int nsegs, port, removed; cpsw_rx_dequeue() local
2728 char port[16]; cpsw_add_sysctls() local
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| /freebsd-src/sys/contrib/device-tree/src/mips/cavium-octeon/ |
| H A D | octeon_3xxx.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
18 /* Fix rx and tx clock transition timing */
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
29 marvell,reg-init =
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| /freebsd-src/contrib/wireguard-tools/man/ |
| H A D | wg.8 | 4 wg - set and retrieve configuration of WireGuard interfaces
29 utility provides a series of sub-commands for changing WireGuard-specific
34 Sub-commands that take an INTERFACE must be passed a WireGuard interface.
39 …-key\fP | \fIprivate-key\fP | \fIlisten-port\fP | \fIfwmark\fP | \fIpeers\fP | \fIpreshared-keys\f…
46 newlines and tabs, meant to be used in scripts. For this script-friendly display,
49 the first contains in order separated by tab: private-key, public-key, listen-port,
51 by tab: public-key, preshared-key, endpoint, allowed-ips, latest-handshake,
52 transfer-rx, transfer-tx, persistent-keepalive.
58 …-port\fP \fI<port>\fP] [\fIfwmark\fP \fI<fwmark>\fP] [\fIprivate-key\fP \fI<file-path>\fP] [\fIpee…
61 for a peer, that peer is removed, not configured. If \fIlisten-port\fP
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| /freebsd-src/sys/contrib/device-tree/src/arm/microchip/ |
| H A D | at91-nattis-2-natte-2.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * at91-nattis-2-natte-2.dts - Device Tree file for the Linea/Nattis board
9 /dts-v1/;
10 #include "at91-linea.dtsi"
11 #include "at91-natte.dtsi"
14 model = "Axentia Linea-Nattis v2 Natte v2";
15 compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
18 gpio-keys {
19 compatible = "gpio-keys";
21 key-wakeup {
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| /freebsd-src/sys/net/ |
| H A D | netmap.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (C) 2011-2014 Matteo Landi, Luigi Rizzo. All rights reserved.
48 * Some fields should be cache-aligned to reduce contention.
56 * --- Netmap data structures ---
68 +---->+---------------+
71 +----------------+ / | other fields |
75 | | / +---------------+
77 | txring_ofs[0] | (rel.to nifp)--' | flags, ptr |
78 | txring_ofs[1] | +---------------+
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| /freebsd-src/lib/libnetmap/ |
| H A D | libnetmap.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 /* if thread-safety is not needed, define LIBNETMAP_NOTHREADSAFE before including
47 * A port open specification (portspec for brevity) has the following syntax
71 * same memory region as the subsystem:indentifier1 port.
78 * -NN bind individual NIC ring pair
79 * @NN open the port in the NN memory region
83 * z zero copy monitor (both tx and rx)
85 * r monitor rx side (copy monitor)
86 * R bind only RX ring(s)
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| /freebsd-src/sys/dev/mana/ |
| H A D | mana_sysctl.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
58 for (i = 0; i < apc->num_queues; i++) { in mana_sysctl_rx_stat_agg_u64()
59 rxq = apc->rxqs[i]; in mana_sysctl_rx_stat_agg_u64()
64 if (err || req->newptr == NULL) in mana_sysctl_rx_stat_agg_u64()
67 for (i = 0; i < apc->num_queues; i++) { in mana_sysctl_rx_stat_agg_u64()
68 rxq = apc->rxqs[i]; in mana_sysctl_rx_stat_agg_u64()
83 rxq = apc->rxqs[0]; in mana_sysctl_rx_stat_u16()
88 if (err || req->newptr == NULL) in mana_sysctl_rx_stat_u16()
103 rxq = apc->rxqs[0]; in mana_sysctl_rx_stat_u32()
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| /freebsd-src/sys/dev/etherswitch/arswitch/ |
| H A D | arswitch_8316.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2011-2012 Stefan Bethke.
76 * + The switch port is GMII/RGMII; in ar8316_hw_setup()
77 * + Port 4 is either connected to the CPU or to the internal switch. in ar8316_hw_setup()
79 if (sc->is_rgmii && sc->phy4cpu) { in ar8316_hw_setup()
80 arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE, in ar8316_hw_setup()
82 device_printf(sc->sc_dev, in ar8316_hw_setup()
83 "%s: MAC port == RGMII, port 4 = dedicated PHY\n", in ar8316_hw_setup()
85 } else if (sc->is_rgmii) { in ar8316_hw_setup()
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| /freebsd-src/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | sc7280-qcard.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
15 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
16 #include <dt-binding
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