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/freebsd-src/sys/contrib/device-tree/Bindings/rtc/
H A Drtc-mt7622.txt1 Device-Tree bindings for MediaTek SoC based RTC
4 - compatible : Should be
5 "mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC
6 - reg : Specifies base physical address and size of the registers;
7 - interrupts : Should contain the interrupt for RTC alarm;
8 - clocks : Specifies list of clock specifiers, corresponding to
9 entries in clock-names property;
10 - clock-names : Should contain "rtc" entries
14 rtc: rtc@10212800 {
15 compatible = "mediatek,mt7622-rtc",
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H A Darmada-380-rtc.txt3 RTC controller for the Armada 38x, 7K and 8K SoCs
6 - compatible : Should be one of the following:
7 "marvell,armada-380-rtc" for Armada 38x SoC
8 "marvell,armada-8k-rtc" for Aramda 7K/8K SoCs
9 - reg: a list of base address and size pairs, one for each entry in
10 reg-names
11 - reg names: should contain:
12 * "rtc" for the RTC registers
13 * "rtc-soc" for the SoC related registers and among them the one
15 - interrupts: IRQ line for the RTC.
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H A Drtc-omap.txt4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
19 - clock-names: Corresponding names of the clocks
[all …]
H A Drtc-mt2712.txt1 Device-Tree bindings for MediaTek SoC based RTC
4 - compatible : Should be "mediatek,mt2712-rtc" : for MT2712 SoC
5 - reg : Specifies base physical address and size of the registers;
6 - interrupts : Should contain the interrupt for RTC alarm;
10 rtc: rtc@10011000 {
11 compatible = "mediatek,mt2712-rtc";
H A Dmicrochip,mfps-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip PolarFire Soc (MPFS) RTC
11 - $ref: rtc.yaml#
14 - Daire McNamara <daire.mcnamara@microchip.com>
15 - Lewis Hanly <lewis.hanly@microchip.com>
20 - microchip,mpfs-rtc
27 - description: |
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H A Dalphascale,asm9260-rtc.txt1 * Alphascale asm9260 SoC Real Time Clock
4 - compatible: Should be "alphascale,asm9260-rtc"
5 - reg: Physical base address of the controller and length
7 - interrupts: IRQ line for the RTC.
8 - clocks: Reference to the clock entry.
9 - clock-names: should contain:
10 * "ahb" for the SoC RTC clock
13 rtc0: rtc@800a0000 {
14 compatible = "alphascale,asm9260-rtc";
17 clock-names = "ahb";
H A Disil,isl12057.txt1 Intersil ISL12057 I2C RTC/Alarm chip
8 ("wakeup-source") to handle the specific use-case found
9 on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104
10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
12 to the SoC but to a PMIC. It allows the device to be powered up when
13 RTC alarm rings. In order to mark the device has a wakeup source and
15 be set when the IRQ#2 pin of the chip is not connected to the SoC but
20 - "compatible": must be "isil,isl12057"
21 - "reg": I2C bus address of the device
25 - "wakeup-source": mark the chip as a wakeup source, independently of
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H A Drtc-mt6397.txt1 Device-Tree bindings for MediaTek PMIC based RTC
3 MediaTek PMIC based RTC is an independent function of MediaTek PMIC that works
4 as a type of multi-function device (MFD). The RTC can be configured and set up
12 ../soc/mediatek/pwrap.txt
15 - compatible: Should be one of follows
16 "mediatek,mt6323-rtc": for MT6323 PMIC
17 "mediatek,mt6358-rtc": for MT6358 PMIC
18 "mediatek,mt6366-rtc", "mediatek,mt6358-rtc": for MT6366 PMIC
19 "mediatek,mt6397-rtc": for MT6397 PMIC
28 rtc {
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H A Drtc-mxc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/rtc-mxc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: rtc.yaml#
13 - Philippe Reynes <tremyfr@gmail.com>
18 - fsl,imx1-rtc
19 - fsl,imx21-rtc
29 - description: input reference
30 - description: the SoC RTC clock
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H A Dxlnx,zynqmp-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/xln
[all...]
H A Dlpc32xx-rtc.txt1 * NXP LPC32xx SoC Real Time Clock controller
4 - compatible: must be "nxp,lpc3220-rtc"
5 - reg: physical base address of the controller and length of memory mapped
7 - interrupts: The RTC interrupt
11 rtc@40024000 {
12 compatible = "nxp,lpc3220-rtc";
H A Ddigicolor-rtc.txt3 This binding currently supports the CX92755 SoC.
6 - compatible: should be "cnxt,cx92755-rtc"
7 - reg: physical base address of the controller and length of memory mapped
9 - interrupts: rtc alarm interrupt
13 rtc@f0000c30 {
14 compatible = "cnxt,cx92755-rtc";
H A Drenesas,sh-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/renesas,sh-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - const: renesas,r7s72100-rtc # RZ/A1H
17 - const: renesas,sh-rtc
25 interrupt-names:
27 - const: alarm
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H A Disil,isl1208.txt1 Intersil ISL1209/19 I2C RTC/Alarm chip with event in
8 - "compatible": Should be one of the following:
9 - "isil,isl1208"
10 - "isil,isl1209"
11 - "isil,isl1218"
12 - "isil,isl1219"
13 - "reg": I2C bus address of the device
16 - "interrupt-names": list which may contains "irq" and "evdet"
18 - "interrupts": list of interrupts for "irq" and "evdet"
20 - "isil,ev-evienb": Enable or disable internal pull on EVIN pin
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/freebsd-src/sys/contrib/device-tree/Bindings/regulator/
H A Dnvidia,tegra-regulators-coupling.txt4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
9 ------------------------
11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
16 ------------------------
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
26 - nvidia,tegra-rtc-regulator: Boolean property that designates regulator
27 as the "RTC domain" voltage regulator.
28 - nvidia,tegra-cpu-regulator: Boolean property that designates regulator
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/freebsd-src/sys/contrib/device-tree/src/arm/moxa/
H A Dmoxart.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* moxart.dtsi - Device Tree Include file for MOXA ART family SoC
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <0>;
28 #address-cells = <1>;
29 #size-cells = <0>;
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/freebsd-src/sys/contrib/device-tree/Bindings/mfd/
H A Dac100.txt1 X-Powers AC100 Codec/RTC IC Device Tree bindings
3 AC100 is a audio codec and RTC subsystem combo IC. The 2 parts are
8 - compatible: "x-powers,ac100"
9 - reg: The I2C slave address or RSB hardware address for the chip
10 - sub-nodes:
11 - codec
12 - compatible: "x-powers,ac100-codec"
13 - interrupts: SoC NMI / GPIO interrupt connected to the
15 - #clock-cells: Shall be 0
16 - clock-output-names: "4M_adda"
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H A Dmediatek,mt6357.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dmt6397.txt4 - Regulator
5 - RTC
6 - Audio codec
7 - GPIO
8 - Clock
9 - LED
10 - Keys
11 - Power controller
16 ../soc/mediatek/mediatek,pwrap.yaml
32 - rtc
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/freebsd-src/sys/contrib/device-tree/Bindings/timer/
H A Dsnps,archs-rtc.txt1 Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs
2 - clocksource provider for UP SoC
6 - compatible : should be "snps,archs-rtc"
7 - clocks : phandle to the source clock
11 rtc {
12 compatible = "snps,arc-rtc";
/freebsd-src/share/man/man4/man4.arm/
H A Daw_rtc.41 .\"-
30 .Nd driver for the real-time clock (RTC) controller in Allwinner SoC
34 device driver provides support for the Allwinner RTC controller.
38 driver supports the RTC controller with any of the following compatible
41 .Bl -bullet -compact
43 allwinner,sun4i-a10-rt
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/freebsd-src/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5 SoC series common device tree source
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
8 * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 soc: soc { label
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/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dlpc1850-creg-clk.txt8 These clocks are used by the RTC and the Event Router peripherals.
13 Documentation/devicetree/bindings/clock/clock-bindings.txt
16 - compatible:
17 Should be "nxp,lpc1850-creg-clk"
18 - #clock-cells:
20 - clocks:
23 The creg-clk node must be a child of the creg syscon node.
32 soc {
34 compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
37 creg_clk: clock-controller {
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/freebsd-src/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-8020.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
9 #include "armada-ap806-dual.dtsi"
10 #include "armada-80x0.dtsi"
14 compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
15 "marvell,armada-ap806";
18 /* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
20 * disable it. However, the RTC clock in CP slave is connected to the
/freebsd-src/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-370-seagate-nas-xbay.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC).
14 #include "armada-370.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
20 stdout-path = "serial0:115200n8";
28 soc {
32 internal-regs {
38 nr-ports = <2>;
44 pinctrl-0 = <&ge0_rgmii_pins>;
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