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/freebsd-src/sys/contrib/libsodium/src/libsodium/crypto_onetimeauth/poly1305/sse2/
H A Dpoly1305_sse2.c109 uint64_t rt0, rt1, rt2, st2, c; in poly1305_init_ext() local
145 rt2 = r2; in poly1305_init_ext()
160 st2 = rt2 * (5 << 2); in poly1305_init_ext()
163 d[1] = ((uint128_t) rt2 * st2) + ((uint128_t)(rt0 * 2) * rt1); in poly1305_init_ext()
164 d[2] = ((uint128_t) rt1 * rt1) + ((uint128_t)(rt2 * 2) * rt0); in poly1305_init_ext()
174 rt2 = (uint64_t) d[2] & 0x3ffffffffff; in poly1305_init_ext()
182 rt2 += c; /* even if rt2 overflows, it will still fit in rp4 safely, and in poly1305_init_ext()
188 R[3] = (uint32_t)((rt1 >> 34) | (rt2 << 10)) & 0x3ffffff; in poly1305_init_ext()
189 R[4] = (uint32_t)((rt2 >> 16)); in poly1305_init_ext()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp983 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1043 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
1055 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2, Addr, in DecodeThreeAddrSRegInstruction()
1066 Rt == Rt2) in DecodeThreeAddrSRegInstruction()
1077 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodeThreeAddrSRegInstruction()
1143 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2, Addr, in DecodeMoveImmInstruction()
1158 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2, Addr, in DecodeUnsignedLdStInstruction()
1171 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt2, Addr, in DecodeUnsignedLdStInstruction()
1184 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt2, Addr, in DecodeUnsignedLdStInstruction()
1197 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt2, Add in DecodeUnsignedLdStInstruction()
1407 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); DecodeExclusiveLdStInstruction() local
1490 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); DecodePairLdStInstruction() local
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/freebsd-src/contrib/llvm-project/lld/ELF/
H A DAArch64ErrataFix.cpp130 // | size (2) 00 | 1000 | o2 L o1 | Rs (5) | o0 | Rt2 (5) | Rn (5) | Rt (5) |
148 // | opc (2) 10 | 1 V 00 | 0 L | imm7 | Rt2 (5) | Rn (5) | Rt (5) |
157 // | opc (2) 10 | 1 V 00 | 1 L | imm7 | Rt2 (5) | Rn (5) | Rt (5) |
165 // | opc (2) 10 | 1 V 01 | 0 L | imm7 | Rt2 (5) | Rn (5) | Rt (5) |
171 // | opc (2) 10 | 1 V 01 | 1 L | imm7 | Rt2 (5) | Rn (5) | Rt (5) |
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2219 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction()
2243 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2247 if (Rt2 == 15) in DecodeAddrMode3Instruction()
2266 if (Rt2 == 15) in DecodeAddrMode3Instruction()
2272 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
2276 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
5799 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); in DecodeVMOVSRR()
5804 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) in DecodeVMOVSRR()
5813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Addres in DecodeVMOVSRR()
2216 unsigned Rt2 = Rt + 1; DecodeAddrMode3Instruction() local
5796 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); DecodeVMOVSRR() local
5822 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); DecodeVMOVRRS() local
5879 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); DecodeT2LDRDPreInstruction() local
5916 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); DecodeT2STRDPreInstruction() local
5985 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); DecodeSwap() local
6196 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); DecoderForMRRC2AndMCRR2() local
6797 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); DecodeMVEVMOVQtoDReg() local
6821 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); DecodeMVEVMOVDRegtoQ() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td1475 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1477 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "",
1478 [(set rGPR:$Rt, rGPR:$Rt2, (ARMldrd t2addrmode_imm8s4:$addr))]>,
1706 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1707 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "",
1708 [(ARMstrd rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr)]>,
1854 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1856 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,
1862 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1864 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2,
[all...]
H A DARMInstrVFP.td1230 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
1231 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
1232 [(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))]>,
1238 bits<4> Rt2;
1244 let Inst{19-16} = Rt2;
1254 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
1259 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
1260 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
1266 bits<4> Rt2;
1272 let Inst{19-16} = Rt2;
[all...]
H A DARMInstrInfo.td2873 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2874 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2997 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
3000 "ldrd", "\t$Rt, $Rt2, $addr!",
3010 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
3013 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
3157 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
3158 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
3331 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
3333 "strd", "\t$Rt, $Rt2,
[all...]
H A DARMInstrFormats.td728 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
730 bits<4> Rt2;
738 let Inst{3-0} = Rt2;
1427 bits<4> Rt2;
1437 let Inst{11-8} = Rt2{3-0};
1446 bits<4> Rt2;
1457 let Inst{11-8} = Rt2{3-0};
H A DARMInstrMVE.td5873 bits<5> Rt2;
5882 let Inst{19-16} = Rt2{3-0};
5920 (ins MQPR:$QdSrc, rGPR:$Rt, rGPR:$Rt2),
5921 0b1, "$Qd$idx, $QdSrc$idx2, $Rt, $Rt2",
5926 def MVE_VMOV_rr_q : MVE_VMOV_64bit<(outs rGPR:$Rt, rGPR:$Rt2), (ins MQPR:$Qd),
5927 0b0, "$Rt, $Rt2, $Qd$idx, $Qd$idx2", ""> {
H A DARMISelLowering.cpp3575 /// ldr rT2, [r0] in LowerGlobalTLSAddressDarwin()
3576 /// blx rT2 in LowerGlobalTLSAddressDarwin()
/freebsd-src/sys/contrib/device-tree/Bindings/sound/
H A Drenesas,rz-ssi.yaml70 MID/RID value of SSI rt2 = 0x25f
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td4503 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
4505 bits<5> Rt2;
4514 let Inst{14-10} = Rt2;
4525 (outs regtype:$Rt, regtype:$Rt2),
4529 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
4530 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
4539 (ins regtype:$Rt, regtype:$Rt2,
4544 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
4545 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
4552 : I<oops, iops, asm, "\t$Rt, $Rt2, [
[all...]
H A DAArch64InstrInfo.td2673 def : Pat<(int_aarch64_stgp (am_indexed7s128 GPR64sp:$Rn, simm7s16:$imm), GPR64:$Rt, GPR64:$Rt2),
2674 (STGPi $Rt, $Rt2, $Rn, $imm)>;
4052 def : Pat<(AArch64stp GPR64z:$Rt, GPR64z:$Rt2, (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)),
4053 (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, simm7s8:$offset)>;
4055 def : Pat<(AArch64stnp FPR128:$Rt, FPR128:$Rt2, (am_indexed7s128 GPR64sp:$Rn, simm7s16:$offset)),
4056 (STNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, simm7s16:$offset)>;
10004 def STILPWpre: BaseLRCPC3IntegerLoadStorePair<0b10, 0b00, 0b0000, (outs GPR64sp:$wback), (ins GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn, #-8]!", "$Rn = $wback">;
10005 def STILPXpre: BaseLRCPC3IntegerLoadStorePair<0b11, 0b00, 0b0000, (outs GPR64sp:$wback), (ins GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [
[all...]
H A DAArch64LoadStoreOptimizer.cpp770 // Which register is Rt and which is Rt2 depends on the offset order. in mergeNarrowZeroStores()
1007 // Which register is Rt and which is Rt2 depends on the offset order. in mergePairedInsns()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp5347 // the Rt == Rt2. All of those are undefined behaviour. in validateInstruction()
5355 unsigned Rt2 = Inst.getOperand(2).getReg(); in validateInstruction()
5360 if (RI->isSubRegisterEq(Rn, Rt2)) in validateInstruction()
5380 unsigned Rt2 = Inst.getOperand(1).getReg(); in validateInstruction()
5381 if (Rt == Rt2) in validateInstruction()
5382 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt"); in validateInstruction()
5393 unsigned Rt2 = Inst.getOperand(2).getReg(); in validateInstruction()
5394 if (Rt == Rt2) in validateInstruction()
5395 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt"); in validateInstruction()
5409 unsigned Rt2 in validateInstruction()
5272 unsigned Rt2 = Inst.getOperand(2).getReg(); validateInstruction() local
5297 unsigned Rt2 = Inst.getOperand(1).getReg(); validateInstruction() local
5310 unsigned Rt2 = Inst.getOperand(2).getReg(); validateInstruction() local
5326 unsigned Rt2 = Inst.getOperand(2).getReg(); validateInstruction() local
5407 unsigned Rt2 = Inst.getOperand(2).getReg(); validateInstruction() local
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/freebsd-src/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp701 uint32_t Rt2 = Bits32(opcode, 14, 10); in EmulateLDPSTP()
707 integer t2 = UInt(Rt2); in EmulateLDPSTP()
699 uint32_t Rt2 = Bits32(opcode, 14, 10); EmulateLDPSTP() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrInfo.td248 : InstSE<(outs), (ins GPR32Opnd:$rt, GPR32Opnd:$rt2, mem_simm12:$addr),
256 : InstSE<(outs GPR32Opnd:$rt, GPR32Opnd:$rt2), (ins mem_simm12:$addr),
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp5904 // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2 in parseMemRegOffsetShift()
5909 .addRegOperands(Inst, 1); // Rt2 in parseMemRegOffsetShift()
6917 // We have to be careful to not emit an invalid Rt2 here, because the rest of in CDEConvertDualRegOperand()
7415 unsigned Rt2 = MRI->getEncodingValue(Reg2); in validatetSTMRegList()
7416 // Rt2 must be Rt + 1. in validatetSTMRegList()
7417 if (Rt + 1 != Rt2) in validatetSTMRegList()
7554 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg()); in validateInstruction()
7567 // Rt2 must be Rt + 1. in validateInstruction()
7568 if (Rt2 != Rt + 1) { in validateInstruction()
7582 if (Rt2 in validateInstruction()
7316 unsigned Rt2 = MRI->getEncodingValue(Reg2); ParseInstruction() local
7437 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg()); validateLDRDSTRD() local
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/freebsd-src/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp10656 // t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = in EmulateLDRDImmediate()
10926 // t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = in EmulateSTRDImm()
11162 uint32_t Rt2 = ReadCoreReg(t2, &success); in EmulateSTRDReg() local
11171 if (!MemAWrite(context, address + 4, Rt2, addr_byte_size)) in EmulateSTRDReg()
13092 "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm8>]!"}, in GetARMOpcodeForInstruction()
13095 "ldrd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"}, in GetARMOpcodeForInstruction()
13139 "strd<c> <Rt>, <Rt2>, [<Rn> #+/-<imm8>]!"}, in GetARMOpcodeForInstruction()
13142 "strd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"}, in GetARMOpcodeForInstruction()
13627 "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm>]!"}, in GetThumbOpcodeForInstruction()
13687 "strd<c> <Rt>, <Rt2>, [<R in GetThumbOpcodeForInstruction()
[all...]
/freebsd-src/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp8470 Value *Rt2 = Builder.CreateLShr(Call, 32); in EmitARMBuiltinExpr()
8471 Rt2 = Builder.CreateTrunc(Rt2, CGF.Int32Ty); in EmitARMBuiltinExpr()
8472 return Rt2; in EmitARMBuiltinExpr()
8689 // the intrinsic has 4 because Rt and Rt2 in EmitARMBuiltinExpr()
8702 Value *Rt2 = Builder.CreateLShr(RtAndRt2, C1); in EmitARMBuiltinExpr()
8703 Rt2 = Builder.CreateTruncOrBitCast(Rt2, Int32Ty); in EmitARMBuiltinExpr()
8705 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm}); in EmitARMBuiltinExpr()
8211 Value *Rt2 = Builder.CreateLShr(Call, 32); EmitAMDGCNBallotForExec() local
8443 Value *Rt2 = Builder.CreateLShr(RtAndRt2, C1); EmitARMBuiltinExpr() local