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/freebsd-src/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7100.dtsi220 resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
250 rstgen: reset-controller@11840000 {
267 resets = <&rstgen JH7100_RSTN_I2C0_APB>;
280 resets = <&rstgen JH7100_RSTN_I2C1_APB>;
293 resets = <&rstgen JH7100_RSTN_GPIO_APB>;
307 resets = <&rstgen JH7100_RSTN_UART2_APB>;
320 resets = <&rstgen JH7100_RSTN_UART3_APB>;
333 resets = <&rstgen JH7100_RSTN_I2C2_APB>;
346 resets = <&rstgen JH7100_RSTN_I2C3_APB>;
359 resets = <&rstgen JH7100_RSTN_WDTIMER_AP
215 rstgen: reset-controller@11840000 { global() label
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/hwmon/
H A Dstarfive,jh71x0-temp.yaml67 resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
68 <&rstgen JH7100_RSTN_TEMP_APB>;
/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra20-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
25 RSTGEN provides the registers needed to control resetting of each block in
H A Dnvidia,tegra124-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
25 RSTGEN provides the registers needed to control resetting of each block in