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/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dmotorcomm,yt8xxx.yaml23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
32 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
33 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
57 drive strength of rx_clk rgmii pad.
58 The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
74 drive strength of rx_data/rx_ctl rgmii pad.
75 The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
97 Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
103 Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
[all …]
H A Dibm,emac.txt5 special McMAL DMA controller, and sometimes an RGMII or ZMII
45 Supported values are: "mii", "rmii", "smii", "rgmii",
47 For Axon on CAB, it is "rgmii"
55 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
56 of the RGMII device node.
57 For Axon: phandle of plb5/plb4/opb/rgmii
58 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
59 RGMII channel is used by this EMAC.
143 phy-mode = "rgmii";
146 rgmii-device = <&RGMII0>;
[all …]
H A Dadi,adin.yaml21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
63 phy-mode = "rgmii-id";
H A Dxlnx,gmii-to-rgmii.yaml4 $id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml#
7 title: Xilinx GMII to RGMII Converter
14 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
24 const: xlnx,gmii-to-rgmii-1.0
55 compatible = "xlnx,gmii-to-rgmii-1.0";
H A Dethernet-controller.yaml78 - rgmii
80 # RGMII with internal RX and TX delays provided by the PHY,
82 - rgmii-id
84 # RGMII with internal RX delay provided by the PHY, the MAC
86 - rgmii-rxid
88 # RGMII with internal TX delay provided by the PHY, the MAC
90 - rgmii-txid
270 - rgmii
271 - rgmii-rxid
272 - rgmii
[all...]
H A Dxilinx_gmii2rgmii.txt5 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
18 - compatible : Should be "xlnx,gmii-to-rgmii-1.0"
31 compatible = "xlnx,gmii-to-rgmii-1.0";
H A Dqcom,ethqos.txt16 - reg-names: Should contain register names "stmmaceth", "rgmii"
21 "ptp_ref", "rgmii"
36 reg-names = "stmmaceth", "rgmii";
37 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
54 phy-mode = "rgmii";
H A Dmediatek-dwmac.txt25 It should be defined for RGMII/MII interface.
28 It should be defined for RGMII/MII interface.
30 Both delay properties need to be a multiple of 170 for RGMII interface,
42 1. tx clock will be inversed in MII/RGMII case,
48 1. rx clock will be inversed in MII/RGMII case.
62 phy-mode ="rgmii-rxid";
H A Dqcom,ethqos.yaml33 - const: rgmii
58 - rgmii
89 reg-names = "stmmaceth", "rgmii";
90 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
112 phy-mode = "rgmii";
H A Damlogic,meson-dwmac.yaml64 The internal RGMII TX clock delay (provided by this driver)
65 in nanoseconds. When phy-mode is set to "rgmii" then the TX
67 set to either "rgmii-id" or "rgmii-txid" the TX clock delay
81 The internal RGMII RX clock delay in nanoseconds. Deprecated, use
175 phy-mode = "rgmii";
H A Dmediatek-dwmac.yaml79 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
83 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
89 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
93 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
112 1. tx clock will be inversed in MII/RGMII case,
122 1. rx clock will be inversed in MII/RGMII case.
159 phy-mode = "rgmii-rxid";
H A Dti,dp83867.yaml25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
81 RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
88 RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
95 PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
97 should use "rgmii-id" if internal delays are desired as this may be
98 changed in future to cause "rgmii" mode to disable delays.
H A Dti,icssg-prueth.yaml110 ti,syscon-rgmii-delay:
118 to ICSSG control register for RGMII transmit delay
216 phy-mode = "rgmii-id";
218 ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
226 phy-mode = "rgmii-id";
228 ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
/freebsd-src/sys/contrib/device-tree/Bindings/net/dsa/
H A Dsja1105.txt19 of support for RGMII internal delays (supported on P/Q/R/S, but not on
33 clock source or sink for this interface (not applicable for RGMII
35 - In the case of RGMII it affects the behavior regarding internal
38 of "rgmii-id", "rgmii-txid" or "rgmii-rxid", then the entity
39 designated to apply the delay/clock skew necessary for RGMII
45 E or T device, it is an error to specify an RGMII phy-mode other
46 than "rgmii" for a port that is in fixed-link mode. In that case,
88 phy-mode = "rgmii-id";
96 phy-mode = "rgmii-id";
104 phy-mode = "rgmii-id";
[all …]
H A Dnxp,sja1105.yaml87 - rgmii
88 - rgmii-rxid
89 - rgmii-txid
90 - rgmii-id
156 phy-mode = "rgmii-id";
164 phy-mode = "rgmii-id";
172 phy-mode = "rgmii-id";
180 phy-mode = "rgmii-id";
188 phy-mode = "rgmii";
H A Dmt7530.txt39 must be either "trgmii" or "rgmii"
54 In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
58 and RGMII delay.
68 2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
76 * mt7621: phy-mode = "rgmii-txid";
77 * mt7623: phy-mode = "rgmii";
157 phy-mode = "rgmii";
169 phy-mode = "rgmii-txid";
228 phy-mode = "rgmii";
247 phy-mode = "rgmii";
[all …]
H A Dmicrochip,lan937x.yaml49 - rgmii
50 - rgmii-id
51 - rgmii-txid
52 - rgmii-rxid
125 phy-mode = "rgmii";
139 phy-mode = "rgmii";
H A Darrow,xrs700x.yaml18 RGMII ports and one RMII port and are managed via i2c or mdio.
54 phy-mode = "rgmii-id";
60 phy-mode = "rgmii-id";
65 phy-mode = "rgmii-id";
/freebsd-src/sys/contrib/device-tree/src/powerpc/
H A Deiger.dts278 RGMII0: emac-rgmii@ef600900 {
279 compatible = "ibm,rgmii-460sx", "ibm,rgmii";
284 RGMII1: emac-rgmii@ef600920 {
285 compatible = "ibm,rgmii-460sx", "ibm,rgmii";
320 phy-mode = "rgmii";
322 rgmii-device = <&RGMII0>;
323 rgmii-channel = <0>;
350 phy-mode = "rgmii";
352 rgmii-device = <&RGMII0>;
353 rgmii-channel = <1>;
[all …]
H A Dklondike.dts131 RGMII0: emac-rgmii@400a2000 {
132 compatible = "ibm,rgmii";
164 phy-mode = "rgmii";
168 rgmii-device = <&RGMII0>;
169 rgmii-channel = <0>;
194 phy-mode = "rgmii";
198 rgmii-device = <&RGMII0>;
199 rgmii-channel = <1>;
H A Dglacier.dts315 RGMII0: emac-rgmii@ef601500 {
316 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
321 RGMII1: emac-rgmii@ef601600 {
322 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
357 phy-mode = "rgmii";
359 rgmii-device = <&RGMII0>;
360 rgmii-channel = <0>;
387 phy-mode = "rgmii";
389 rgmii-device = <&RGMII0>;
390 rgmii-channel = <1>;
[all …]
H A Drainier.dts252 RGMII0: emac-rgmii@ef601000 {
253 compatible = "ibm,rgmii-440grx", "ibm,rgmii";
277 phy-mode = "rgmii";
281 rgmii-device = <&RGMII0>;
282 rgmii-channel = <0>;
306 phy-mode = "rgmii";
310 rgmii-device = <&RGMII0>;
311 rgmii-channel = <1>;
H A Dobs600.dts238 RGMII0: emac-rgmii@ef600b00 {
239 compatible = "ibm,rgmii-405ex", "ibm,rgmii";
266 phy-mode = "rgmii";
268 rgmii-device = <&RGMII0>;
269 rgmii-channel = <0>;
296 phy-mode = "rgmii";
298 rgmii-device = <&RGMII0>;
299 rgmii-channel = <1>;
/freebsd-src/sys/contrib/device-tree/src/arm/nxp/ls/
H A Dls1021a-tsn.dts62 phy-mode = "rgmii-id";
70 phy-mode = "rgmii-id";
78 phy-mode = "rgmii-id";
86 phy-mode = "rgmii-id";
93 phy-mode = "rgmii";
121 /* RGMII delays added via PCB traces */
123 phy-mode = "rgmii";
/freebsd-src/sys/dev/etherswitch/arswitch/
H A Darswitch_8316.c76 * + The switch port is GMII/RGMII; in ar8316_hw_setup()
83 "%s: MAC port == RGMII, port 4 = dedicated PHY\n", in ar8316_hw_setup()
89 "%s: MAC port == RGMII, port 4 = switch port\n", in ar8316_hw_setup()
104 * If port 4 is RGMII, force workaround in ar8316_hw_setup()
108 "%s: port 4 RGMII workaround\n", in ar8316_hw_setup()
111 /* work around for phy4 rgmii mode */ in ar8316_hw_setup()

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