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/freebsd-src/sys/contrib/device-tree/Bindings/usb/
H A Dnxp,ptn36502.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Donnn,nb7vpq904m.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd-src/sys/dev/al_eth/
H A Dal_init_eth_lm.c1 /*-
45 /* delay before checking link status after reconfiguring the retimer (uSec) */
73 /* 40GBASE-LR4 and 40GBASE-SR4 are optic modules */
79 #define AL_ETH_LM_RETIMER_WAIT_FOR_LOCK 500 /* delay after retimer reset to lock (mSec) */
185 /* Enable loop filter auto-adjust */
195 /* Set Main-cursor tap sign to positive (6.12) */
197 /* Set Post-cursor tap sign to negative (6.12) */
199 /* Set Pre-cursor tap sign to negative (6.12) */
201 /* Set Main-cursor tap magnitude to 13 (6.12) */
222 static struct al_eth_lm_retimer retimer[] = { variable
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H A Dal_eth.c1 /*-
120 #define AL_ETH_MAC_TABLE_DROP_IDX (AL_ETH_FWD_MAC_NUM - 1)
121 #define AL_ETH_MAC_TABLE_BROADCAST_IDX (AL_ETH_MAC_TABLE_DROP_IDX - 1)
175 #define AL_RX_LOCK_INIT(_sc) mtx_init(&((_sc)->if_rx_lock), "ALRXL", "ALRXL", MTX_DEF)
176 #define AL_RX_LOCK(_sc) mtx_lock(&((_sc)->if_rx_lock))
177 #define AL_RX_UNLOCK(_sc) mtx_unlock(&((_sc)->if_rx_lock))
231 /* flag for napi-like mbuf processing, controlled from sysctl */
291 CTLFLAG_RW, &napi, 0, "Use pseudo-napi mechanism"); in al_attach()
294 adapter->dev = dev; in al_attach()
295 adapter->board_typ in al_attach()
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/freebsd-src/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm8550-qrd.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
23 compatible = "qcom,sm8550-qrd", "qcom,sm8550";
24 chassis-typ
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H A Dqrb5165-rb5.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10 #include <dt-bindings/sound/qcom,q6afe.h>
11 #include <dt-binding
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/freebsd-src/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
78- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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