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/freebsd-src/sys/contrib/device-tree/src/arm64/apple/
H A Dt8103-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 ps_sbr: power-controller@100 {
11 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
13 #power-domain-cells = <0>;
14 #reset-cells = <0>;
16 apple,always-on; /* Core device */
19 ps_aic: power-controller@108 {
20 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
22 #power-domain-cells = <0>;
23 #reset-cells = <0>;
[all …]
H A Dt8112-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 ps_sbr: power-controller@100 {
11 compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";
13 #power-domain-cells = <0>;
14 #reset-cells = <0>;
16 apple,always-on; /* Core device */
19 ps_aic: power-controller@108 {
20 compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";
22 #power-domain-cells = <0>;
23 #reset-cells = <0>;
[all …]
H A Dt600x-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 DIE_NODE(ps_pms_bridge): power-controller@100 {
10 compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 DIE_NODE(ps_aic): power-controller@108 {
19 compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/reset/
H A Dti,sci-reset.txt1 Texas Instruments System Control Interface (TI-SCI) Reset Controller
4 Some TI SoCs contain a system controller (like the Power Management Micro
5 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
7 between the host processor running an OS and the system controller happens
8 through a protocol called TI System Control Interface (TI-SCI protocol).
12 TI-SCI Reset Controller Node
14 This reset controller node uses the TI SCI protocol to perform the reset
16 node of the associated TI-SCI system controller node.
19 --------------------
20 - compatible : Should be "ti,sci-reset"
[all …]
H A Damlogic,meson-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/reset/amlogic,meson-rese
[all...]
H A Dti-syscon-reset.txt1 TI SysCon Reset Controller
4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
6 typically provided by means of memory-mapped I/O registers. These registers are
12 A SysCon Reset Controller node defines a device that uses a syscon node
13 and provides reset management functionality for various hardware modules
16 SysCon Reset Controller Node
18 Each of the reset provider/controller nodes should be a child of a syscon
22 --------------------
23 - compatible : Should be,
[all …]
H A Dti,sci-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/t
[all...]
H A Dcanaan,k210-rst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/canaan,k210-rst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan Kendryte K210 Reset Controller
10 - Damien Le Moal <dlemoal@kernel.org>
13 Canaan Kendryte K210 reset controller driver which supports the SoC
14 system controller supplied reset registers for the various peripherals
15 of the SoC. The K210 reset controller node must be defined as a child
16 node of the K210 system controller node.
[all …]
H A Dhisilicon,hi6220-reset.txt1 Hisilicon System Reset Controller
4 Please also refer to reset.txt in this directory for common reset
5 controller binding usage.
7 The reset controller registers are part of the system-ctl block on
11 - compatible: should be one of the following:
12 - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
13 - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
14 - "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller.
15 - reg: should be register base and length as documented in the
17 - #reset-cells: 1, see below
[all …]
H A Dsnps,dw-reset.txt1 Synopsys DesignWare Reset controller
4 Please also refer to reset.txt in this directory for common reset
5 controller binding usage.
9 - compatible: should be one of the following.
10 "snps,dw-high-reset" - for active high configuration
11 "snps,dw-low-reset" - for active low configuration
13 - reg: physical base address of the controller and length of memory mapped
16 - #reset-cells: must be 1.
20 dw_rst_1: reset-controller@0000 {
21 compatible = "snps,dw-high-reset";
[all …]
H A Dbrcm,brcmstb-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB SW_INIT-style reset controller
10 Broadcom STB SoCs have a SW_INIT-style reset controller with separate
12 reset lines.
14 Please also refer to reset.txt in this directory for common reset
15 controller binding usage.
18 - Florian Fainelli <f.fainelli@gmail.com>
[all …]
H A Dbrcm,brcmstb-reset.txt1 Broadcom STB SW_INIT-style reset controller
4 Broadcom STB SoCs have a SW_INIT-style reset controller with separate
6 reset lines.
8 Please also refer to reset.txt in this directory for common reset
9 controller binding usage.
12 - compatible: should be brcm,brcmstb-reset
13 - reg: register base and length
14 - #reset-cells: must be set to 1
18 reset: reset-controller@8404318 {
19 compatible = "brcm,brcmstb-reset";
[all …]
H A Dst,sti-powerdown.txt1 STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
4 This binding describes a reset controller device that is used to enable and
5 disable on-chip peripheral controllers such as USB and SATA, using
7 registers. These have been grouped together into a single reset controller
15 Please refer to reset.txt in this directory for common reset
16 controller binding usage.
19 - compatible: Should be "st,stih407-powerdown"
20 - #reset-cells: 1, see below
24 powerdown: powerdown-controller {
25 compatible = "st,stih407-powerdown";
[all …]
H A Dfsl,imx7-src.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7 System Reset Controller
10 - Andrey Smirnov <andrew.smirnov@gmail.com>
13 The system reset controller can be used to reset various set of
14 peripherals. Device nodes that need access to reset lines should
15 specify them as a reset phandle in their corresponding node as
16 specified in reset.txt.
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
[all …]
/freebsd-src/share/man/man4/
H A Dtwe.4
/freebsd-src/sys/contrib/device-tree/Bindings/pci/
H A Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC PCIe RP/EP controller
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
[all …]
H A Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/mfd/
H A Dcanaan,k210-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysct
[all...]
H A Daltera-a10sr.txt4 - compatible : "altr,a10sr"
5 - spi-max-frequency : Maximum SPI frequency.
6 - reg : The SPI Chip Select address for the Arria10
8 - interrupts : The interrupt line the device is connected to.
9 - interrupt-controller : Marks the device node as an interrupt controller.
10 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
13 masks from ../interrupt-controller/interrupts.txt.
15 The A10SR consists of these sub-devices:
18 ------ ----------
19 a10sr_gpio GPIO Controller
[all …]
H A Daspeed-lpc.txt2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
7 primary use case of the Aspeed LPC controller is as a slave on the bus
8 (typically in a Baseboard Management Controller SoC), but under certain
11 The LPC controller is represented as a multi-function device to account for the
14 * An IPMI Block Transfer[2] Controller
16 * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
18 APB-to-LPC bridging amonst other functions.
20 * An LPC Host Interface Controller: Manages functions exposed to the host such
21 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
[all …]
H A Daspeed-lpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Aspeed Low Pin Count (LPC) Bus Controller
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
17 primary use case of the Aspeed LPC controller is as a slave on the bus
18 (typically in a Baseboard Management Controller SoC), but under certain
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/keystone/
H A Dti,sci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm/socionext/
H A Duniphier-pro4.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-pro4";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-g12.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-g12
[all...]

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