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/freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmips-gic.txt4 It also supports local (per-processor) interrupts and software-generated
5 interrupts which can be used as IPIs. The GIC also includes a free-running
6 global timer, per-CPU count/compare timers, and a watchdog.
9 - compatible : Should be "mti,gic".
10 - interrupt-controller : Identifies the node as an interrupt controller
11 - #interrupt-cells : Specifies the number of cells needed to encode an
13 - The first cell is the type of interrupt, local or shared.
14 See <include/dt-bindings/interrupt-controller/mips-gic.h>.
15 - The second cell is the GIC interrupt number.
16 - The third cell encodes the interrupt flags.
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H A Dmti,gic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
23 "#interrupt-cells":
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/freebsd-src/sys/arm/arm/
H A Dmachdep.c3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
7 * Copyright (c) 1994-1998 Mark Brinicombe.
9 * All rights reserved.
56 #include <sys/cpu.h>
150 * relocate the vectors.
160 unsigned int *vectors in arm_vector_init() local
262 cpu_idle_wakeup(int cpu) cpu_idle_wakeup() argument
394 set_stackptrs(int cpu) set_stackptrs() argument
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H A Dexception.S3 /*-
4 * Copyright (c) 1994-1997 Mark Brinicombe.
6 * All rights reserved.
41 * Low level handlers for exception vectors
77 * PUSHFRAME - macro to push a trap frame on the stack in the current mode
82 str lr, [sp, #-4]!; /* Push the return address */ \
84 stmia sp, {r0-r12}; /* Push the user mode registers */ \
86 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
89 str r0, [sp, #-4]!;
92 * PULLFRAME - macr
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/freebsd-src/sys/contrib/device-tree/Bindings/powerpc/
H A Dibm,powerpc-cpu-features.txt3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
12 This device tree binding describes CPU features available to software, with
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
24 Description: Container of CPU feature nodes.
26 The node name must be "ibm,powerpc-cpu-features".
35 - compatible
38 Definition: "ibm,powerpc-cpu-features"
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/freebsd-src/sys/x86/include/
H A Dintr_machdep.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
39 * IDT vectors, but all other device interrupts allocate IDT vectors
40 * on demand. Currently we have 191 IDT vectors available for device
41 * interrupts on each CPU. On many systems with I/O APICs, a lot of
42 * the IRQs are not used, so the total number of IRQ values reserved
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/freebsd-src/share/man/man4/
H A Dnvme.42 .\" Copyright (c) 2012-2016 Intel Corporation
3 .\" All rights reserved.
43 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
65 .Bl -bullet
69 Per-CPU IO queue pairs
93 will create an I/O queue pair for each CPU, provide
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H A Daesni.42 .\" All rights reserved.
35 .Bd -ragged -offset indent
44 .Bd -literal -offset indent
68 driver does not attach on systems that lack both CPU capabilities.
79 is data-independent, thus eliminating some attack vectors based on
80 measuring cache use and timings typically present in table-driven
99 .An -nosplit
/freebsd-src/sys/arm/nvidia/tegra124/
H A Dtegra124_mp.c1 /*-
3 * All rights reserved.
37 #include <machine/cpu.h>
53 #define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 /* exception vectors */
71 mp_maxid = ncpu - 1; in tegra124_mp_setmaxid()
87 panic("Couldn't map the exception vectors\n"); in tegra124_mp_start_ap()
101 mask = 1 << (i + 8); /* cpu mask */ in tegra124_mp_start_ap()
112 /* Wait until CPU is powered */ in tegra124_mp_start_ap()
/freebsd-src/sys/dev/cxgbe/firmware/
H A Dt5fw_cfg_fpga.txt3 # Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
33 # their SR-IOV Capabilities.
[all …]
H A Dt6fw_cfg_fpga.txt3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
37 # 8. Some customers will want to support large CPU count systems with
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
[all …]
H A Dt4fw_cfg_uwire.txt3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
33 # their SR-IOV Capabilities.
[all …]
H A Dt5fw_cfg_uwire.txt3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 4-port T5-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
37 # 8. Some customers will want to support large CPU count systems with
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 8 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
[all …]
H A Dt6fw_cfg_uwire.txt3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
37 # 8. Some customers will want to support large CPU count systems with
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
[all …]
/freebsd-src/sys/dev/acpica/
H A Dacpi_hpet.c1 /*-
2 * Copyright (c) 2005 Poul-Henning Kamp
4 * All rights reserved.
108 uint32_t vectors; member
142 sc = tc->tc_priv; in hpet_get_timecount()
143 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); in hpet_get_timecount()
151 sc = tc->tc_priv; in hpet_vdso_timehands()
152 vdso_th->th_algo = VDSO_TH_ALGO_X86_HPET; in hpet_vdso_timehands()
153 vdso_th->th_x86_shift = 0; in hpet_vdso_timehands()
154 vdso_th->th_x86_hpet_idx = device_get_unit(sc->dev); in hpet_vdso_timehands()
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/freebsd-src/sys/x86/x86/
H A Dmsi.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
5 * All rights reserved.
16 * 3. Neither the name of the author nor the names of any co-contributors
93 (MSI_INTEL_ADDR_BASE | (msi)->msi_cpu << 12 | \
96 (MSI_INTEL_DATA_TRGREDG | MSI_INTEL_DATA_DELFIXED | (msi)->msi_vector)
111 * For MSI-
406 u_int cpu, domain, *mirqs; msi_alloc() local
661 u_int cpu, domain; msix_alloc() local
[all...]
H A Dlocal_apic.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
5 * All rights reserved.
15 * 3. Neither the name of the author nor the names of any co-contributors
91 /* Sanity checks on IDT vectors. */
98 * I/O interrupts use non-negative IRQ values. These values are used
99 * to mark unused IDT entries or IDT entries reserved fo
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/freebsd-src/share/doc/smm/02.config/
H A D2.t2 .\" The Regents of the University of California. All rights reserved.
60 indicates if the system is going to operate on a DEC VAX-11\(dg computer,
73 .I "cpu type"
74 indicates which, of possibly many, cpu's the system is to operate on.
75 For example, if the system is being configured for a VAX-11, it could
76 be running on a VAX 8600, VAX-11/780, VAX-11/750, VAX-11/730 or MicroVAX II.
77 (Other VAX cpu types, including the 8650, 785 and 725, are configured using
78 the cpu designation for compatible machines introduced earlier.)
80 more than one cpu type implies that the system should be configured to run
81 on any of the cpu's specified. For some types of machines this is not
[all …]
H A D4.t2 .\" The Regents of the University of California. All rights reserved.
61 .IP "\fBcpu\fP ``\fItype\fP''"
63 This system is to run on the cpu type specified.
64 More than one cpu type specification
80 \-DFUNNY \-DHAHA in the resultant makefile.
123 This is usually a cute name like ERNIE (short for Ernie Co-Vax) or
142 \fBconfig\fP\ \fIsysname\fP\ \fIconfig-clauses\fP
161 \fBroot\fP [ \fBon\fP ] \fIroot-device\fP
162 \fBswap\fP [ \fBon\fP ] \fIswap-device\fP [ \fBand\fP \fIswap-device\fP ] ...
163 \fBdumps\fP [ \fBon\fP ] \fIdump-device\fP
[all …]
/freebsd-src/sys/amd64/vmm/
H A Dvmm_lapic.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * All rights reserved.
57 * vectors 16 through 255 can be delivered through the local APIC. in lapic_set_intr()
73 int cpu, error; in lapic_set_local_intr()
78 CPU_FOREACH_ISSET(cpu, &dmask) { in lapic_set_local_intr()
79 vlapic = vm_lapic(vm_vcpu(vm, cpu)); in lapic_set_local_intr()
72 int cpu, error; lapic_set_local_intr() local
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/freebsd-src/sys/net/
H A Diflib.c1 /*-
2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
3 * All rights reserved.
102 * Enable mbuf vectors for compressing long mbuf chains
107 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
112 * - small packet forwarding which is just returning a single mbuf to
119 * - private structures
120 * - ifli
4911 find_child_with_core(int cpu,struct cpu_group * grp) find_child_with_core() argument
4934 find_l2_neighbor(int cpu) find_l2_neighbor() argument
4977 find_l2_neighbor(int cpu) find_l2_neighbor() argument
5839 int i, j, cpu, err, txconf, rxconf; iflib_queues_alloc() local
6499 iflib_io_tqg_attach(struct grouptask * gt,void * uniq,int cpu,const char * name) iflib_io_tqg_attach() argument
6607 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; iflib_msix_init() local
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/freebsd-src/sys/contrib/device-tree/src/mips/ralink/
H A Dmt7621.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 #include <dt-bindings/interrupt-controller/mips-gic.h>
3 #include <dt-binding
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/freebsd-src/sys/contrib/alpine-hal/
H A Dal_hal_nb_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
310 /* [0x20] Specifies the state of the CPU with reference to power modes. */
463 /* Defines the internal CPU GIC operating frequency ratio with the main CPU clock.
472 /* Disables the GIC CPU interface logic and routes the legacy nIRQ, nFIQ, nVIRQ, and nVFIQ
474 0 Enable the GIC CPU interface logic.
[all …]
/freebsd-src/lib/libcrypt/
H A Dcrypt-sha256.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2011 The FreeBSD Project. All rights reserved.
29 * SHA256-based Unix crypt implementation. Released into the Public Domain by
80 if (strncmp(sha256_salt_prefix, salt, sizeof(sha256_salt_prefix) - 1) == 0) in crypt_sha256()
82 salt += sizeof(sha256_salt_prefix) - 1; in crypt_sha256()
84 if (strncmp(salt, sha256_rounds_prefix, sizeof(sha256_rounds_prefix) - in crypt_sha256()
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H A Dcrypt-sha512.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2011 The FreeBSD Project. All rights reserved.
29 * SHA512-based Unix crypt implementation. Released into the Public Domain by
80 if (strncmp(sha512_salt_prefix, salt, sizeof(sha512_salt_prefix) - 1) == 0) in crypt_sha512()
82 salt += sizeof(sha512_salt_prefix) - 1; in crypt_sha512()
84 if (strncmp(salt, sha512_rounds_prefix, sizeof(sha512_rounds_prefix) - in crypt_sha512()
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