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/llvm-project/llvm/docs/AMDGPU/
H A D	AMDGPUAsmGFX940.rst	23 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`. 28 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this … 41 …ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` … 42 …ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` … 43 …ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`,… 44 …ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`,… 45 …ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`,… 46 …ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`,… 47 …ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` … 48 …ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` … [all …]
H A D	AMDGPUAsmGFX8.rst	23 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`. 28 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this … 41 …ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx8_vdata_6802ce>` … 42 …ref:`vdst<amdgpu_synid_gfx8_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>`, … 43 …ref:`vdst<amdgpu_synid_gfx8_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>`, … 44 …ref:`vdst<amdgpu_synid_gfx8_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>`, … 45 … :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` :ref:`o… 46 … :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` :ref:`o… 47 … :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` :ref:`o… 48 …ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx8_vdata_6802ce>` … [all …]
H A D	AMDGPUAsmGFX1030.rst	25 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`. 30 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this … 43 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`vsr… 44 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802… 45 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802… 46 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802… 47 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802… 48 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802… 49 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802c… 50 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802c… [all …]
H A D	AMDGPUAsmGFX9.rst	23 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`. 28 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this … 41 …ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_6802ce>` … 42 …ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, … 43 …ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, … 44 …ref:`vdst<amdgpu_synid_gfx9_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, … 45 … :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` :ref:`o… 46 … :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` :ref:`o… 47 … :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` :ref:`o… 48 …ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_6802ce>` … [all …]
H A D	AMDGPUAsmGFX11.rst	25 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`. 30 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this … 43 …:ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx11_vdata_6802ce>` … 44 …ref:`vdst<amdgpu_synid_gfx11_vdst_bdb32f>`::ref:`b64<amdgpu_synid_gfx11_type_deviation_a14eb1>`, … 45 …ref:`vdst<amdgpu_synid_gfx11_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee… 46 …ref:`vdst<amdgpu_synid_gfx11_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee… 47 …ref:`vdst<amdgpu_synid_gfx11_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee… 48 …:ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx11_vdata_6802ce>` … 49 …:ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx11_vdata_fd235e>` … 50 …:ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx11_vdata_6802ce>` … [all …]
H A D	AMDGPUAsmGFX10.rst	23 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`. 28 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this … 41 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<a… 42 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`… 43 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`… 44 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`… 45 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`… 46 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`… 47 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` … 48 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`:… [all …]
H A D	AMDGPUAsmGFX90a.rst	23 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`. 28 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this … 41 …ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_be4895>` … 42 …ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_9ad749>` … 43 …ref:`vdst<amdgpu_synid_gfx90a_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`,… 44 …ref:`vdst<amdgpu_synid_gfx90a_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`,… 45 …ref:`vdst<amdgpu_synid_gfx90a_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`,… 46 …ref:`vdst<amdgpu_synid_gfx90a_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`,… 47 …ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_be4895>` … 48 …ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_9ad749>` … [all …]
H A D	AMDGPUAsmGFX7.rst	23 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`. 28 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this … 41 …ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>`, … 42 …ref:`vdst<amdgpu_synid_gfx7_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>`, … 43 … :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` :ref:`o… 44 … :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` :ref:`o… 45 …ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>` … 46 …ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx7_vdata_fd235e>` … 47 …ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>` … 48 …ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx7_vdata_fd235e>` … [all …]
H A D	AMDGPUAsmGFX908.rst	25 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`. 30 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this … 43 …ref:`vaddr<amdgpu_synid_gfx908_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx908_vdata_6802ce>`, … 44 …ref:`vaddr<amdgpu_synid_gfx908_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx908_vdata_6802ce>`, … 53 …ref:`vdata<amdgpu_synid_gfx908_vdata_fe1edf>`, :ref:`vaddr<amdgpu_synid_gfx908_vaddr_b73dc0>`, … 54 …ref:`vdata<amdgpu_synid_gfx908_vdata_fe1edf>`, :ref:`vaddr<amdgpu_synid_gfx908_vaddr_b73dc0>`, … 63 …ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`… 64 …ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref… 65 …ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`… 66 …ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref… [all …]
H A D	AMDGPUAsmGFX906.rst	25 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`. 30 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this … 43 …v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_… 44 …ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx906_vsrc>`::ref:`m<amdgpu_sy… 45 …v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_… 46 …ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx906_vsrc>`, :ref:`vsrc1<a… 47 …ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_gfx906_src_1>`::ref:`m<amdgpu_sy… 56 …ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_gfx906_src_2>`::ref:`m<amdgpu_sy… 57 …_xnor_b32_e64 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_g… 66 …ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_gfx906_src_2>`::ref:`f16x2<amdgpu… [all …]
H A D	AMDGPUAsmGFX1011.rst	25 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`. 30 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this … 43 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx1011_vsrc>`::ref:`f16x2<amdg… 44 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx1011_vsrc>`::ref:`i8x4<amdgp… 53 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx1011_vsrc>`::ref:`f16x2<amd… 54 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx1011_vsrc>`::ref:`i8x4<amdg… 63 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid_gfx1011_src>`::ref:`f16x2<amdgp… 64 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid_gfx1011_src>`::ref:`i8x4<amdgpu… 73 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid_gfx1011_src>`::ref:`f16x2<amdgp… 74 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid_gfx1011_src_2>`::ref:`i16x2<amd… [all …]
/llvm-project/llvm/test/MC/WebAssembly/
H A D	weak-alias.s	`2 …own-unknown -mattr=+reference-types -filetype=obj < %s \| obj2yaml \| FileCheck --check-prefix=REF %s 247 # REF: - Type: TYPE 248 # REF-NEXT: Signatures: 249 # REF-NEXT: - Index: 0 250 # REF-NEXT: ParamTypes: [] 251 # REF-NEXT: ReturnTypes: 252 # REF-NEXT: - I32 253 # REF-NEXT: - Type: IMPORT 254 # REF-NEXT: Imports: 255 # REF-NEXT: - Module: env [all …]`
/llvm-project/flang/test/Lower/
H A D	namelist.f90	11 ! CHECK: %[[V_7:[0-9]+]] = fir.declare %[[V_5]](%[[V_6]]) typeparams %c3{{.}} {uniq_name = "_QFEccc"} : (!fir.ref<!fir.array<4x!fir.char<1,3>>>, !fir.shape<1>, index) -> !fir.ref<!fir.array<4x!fir.char<1,3>>> 13 ! CHECK: %[[V_9:[0-9]+]] = fir.declare %[[V_8]] {uniq_name = "_QFEjjj"} : (!fir.ref<i32>) -> !fir.ref<i32> 14 ! CHECK: fir.store %c17{{.}} to %[[V_9]] : !fir.ref<i32> 21 ! CHECK: %[[V_24:[0-9]+]] = fir.alloca !fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> 22 ! CHECK: %[[V_25:[0-9]+]] = fir.undefined !fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> 23 ! CHECK: %[[V_26:[0-9]+]] = fir.address_of(@_QQclX6A6A6A00) : !fir.ref<!fi [all...]
H A D	io-derived-type.f90	39 ! CHECK: %[[V_15:[0-9]+]] = fir.coordinate_of %{{.}}, %[[V_14]] : (!fir.ref<!fir.type<_QMmTt{n:i32}>>, !fir.field) -> !fir.ref<i32> 40 ! CHECK: fir.store %c1{{.}} to %[[V_15]] : !fir.ref<i32> 41 ! CHECK: %[[V_16:[0-9]+]] = fir.embox %{{.*}} : (!fir.ref<!fir.type<_QMmTt{n:i32}>>) -> !fir.box<!fir.type<_QMmTt{n:i32}>> 43 ! CHECK: %[[V_18:[0-9]+]] = fir.address_of(@_QQMmFtest1.nonTbpDefinedIoTable) : !fir.ref<tuple<i64, !fir.ref<!fir.array<1xtuple<!fir.ref<none>, !fir.ref<none>, i32, i1>>>, i1>> 44 ! CHECK: %[[V_19:[0-9]+]] = fir.convert %[[V_18]] : (!fir.ref<tuple<i64, !fir.ref<!fi [all...]
/llvm-project/flang/test/Lower/OpenMP/
H A D	threadprivate-integer-different-kinds.f90	15 !CHECK-DAG: %[[I:.]] = fir.address_of(@_QFEi) : !fir.ref<i32> 16 …]]:2 = hlfir.declare %[[I]] {uniq_name = "_QFEi"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i3… 17 !CHECK-DAG: %[[OMP_I:.]] = omp.threadprivate %[[I_DECL]]#1 : !fir.ref<i32> -> !fir.ref<i32> 18 … = hlfir.declare %[[OMP_I]] {uniq_name = "_QFEi"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i3… 19 !CHECK-DAG: %[[I1:.]] = fir.address_of(@_QFEi1) : !fir.ref<i8> 20 …]:2 = hlfir.declare %[[I1]] {uniq_name = "_QFEi1"} : (!fir.ref<i8>) -> (!fir.ref<i8>, !fir.ref<i8>) 21 !CHECK-DAG: %[[OMP_I1:.]] = omp.threadprivate %[[I1_DECL]]#1 : !fir.ref<i8> -> !fir.ref<i8> 22 …= hlfir.declare %[[OMP_I1]] {uniq_name = "_QFEi1"} : (!fir.ref<i8>) -> (!fir.ref<i8>, !fir.ref<i8>) 23 !CHECK-DAG: %[[I16:.*]] = fir.address_of(@_QFEi16) : !fir.ref<i128> 24 …= hlfir.declare %[[I16]] {uniq_name = "_QFEi16"} : (!fir.ref<i128>) -> (!fir.ref<i128>, !fir.ref<i… [all …]
H A D	parallel-firstprivate-clause-scalar.f90	7 !CHECK: omp.private {type = firstprivate} @[[ARG2_LOGICAL_PRIVATIZER:_QFfirstprivate_logicalEarg2_firstprivate_ref_l8]] : !fir.ref<!fir.logical<1>> alloc 9 !CHECK: omp.private {type = firstprivate} @[[ARG1_LOGICAL_PRIVATIZER:_QFfirstprivate_logicalEarg1_firstprivate_ref_l32]] : !fir.ref<!fir.logical<4>> alloc { 10 !CHECK: ^bb0(%{{.}}: !fir.ref<!fir.logical<4>>): 13 !CHECK: omp.yield(%[[PVT_DECL]]#0 : !fir.ref<!fir.logical<4>>) 15 !CHECK: ^bb0(%[[ORIG_REF:.]]: !fir.ref<!fir.logical<4>>, %[[PVT_REF:.]]: !fir.ref<!fir.logical<4>>): 18 !CHECK: omp.yield(%[[PVT_REF]] : !fir.ref<!fir.logical<4>>) 21 !CHECK: omp.private {type = firstprivate} @[[ARG2_COMPLEX_PRIVATIZER:_QFfirstprivate_complexEarg2_firstprivate_ref_z64]] : !fir.ref<complex<f64>> alloc 23 !CHECK: omp.private {type = firstprivate} @[[ARG1_COMPLEX_PRIVATIZER:_QFfirstprivate_complexEarg1_firstprivate_ref_z32]] : !fir.ref<complex<f32>> alloc { 24 !CHECK: ^bb0(%{{.}}: !fir.ref<comple [all...]
H A D	copyin.f90	9 ! CHECK: %[[VAL_0:.]] = fir.address_of(@_QFcopyin_scalar_arrayEx1) : !fir.ref<i32> 10 ! CHECK: %[[VAL_1:.]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFcopyin_scalar_arrayEx1"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i32>) 11 ! CHECK: %[[VAL_2:.]] = omp.threadprivate %[[VAL_1]]#1 : !fir.ref<i32> -> !fir.ref<i32> 12 ! CHECK: %[[VAL_3:.]]:2 = hlfir.declare %[[VAL_2]] {uniq_name = "_QFcopyin_scalar_arrayEx1"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i32>) 13 ! CHECK: %[[VAL_4:.*]] = fir.address_of(@_QFcopyin_scalar_arrayEx2) : !fir.ref<!fi [all...]
H A D	copyprivate.f90	`5 !CHECK-DAG: func private @_copy_i64(%{{.}}: !fir.ref<i64>, %{{.}}: !fir.ref<i64>) 6 !CHECK-DAG: func private @_copy_f32(%{{.}}: !fir.ref<f32>, %{{.}}: !fir.ref<f32>) 7 !CHECK-DAG: func private @_copy_f64(%{{.}}: !fir.ref<f64>, %{{.}}: !fir.ref<f64>) 8 !CHECK-DAG: func private @_copy_z32(%{{.}}: !fir.ref<complex<f32>>, %{{.}}: !fir.ref<complex<f32>>) 9 !CHECK-DAG: func private @_copy_z64(%{{.}}: !fir.ref<complex<f64>>, %{{.}}: !fir.ref<comple [all...]`
H A D	threadprivate-commonblock.f90	19 !CHECK-DAG: %[[CBLK_ADDR:.]] = fir.address_of(@blk_) : !fir.ref<!fir.array<103xi8>> 20 !CHECK-DAG: %[[CBLK_ADDR_CVT:.]] = fir.convert %[[CBLK_ADDR]] : (!fir.ref<!fir.array<103xi8>>) -> !fir.ref<!fir.array<?xi8>> 21 !CHECK-DAG: %[[A_ADDR:.]] = fir.coordinate_of %[[CBLK_ADDR_CVT]], %c0 : (!fir.ref<!fir.array<?xi8>>, index) -> !fir.ref<i8> 22 !CHECK-DAG: %[[A_ADDR_CVT:.]] = fir.convert %[[A_ADDR]] : (!fir.ref<i8>) -> !fir.ref<i32> 23 !CHECK-DAG: %[[A_VAL:.*]]:2 = hlfir.declare %[[A_ADDR_CVT]] {uniq_name = "_QMtestEa"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i3 [all...]
H A D	implicit-dsa.f90	9 ! CHECK-SAME: {type = private} @[[TEST6_Y_PRIV:.]] : !fir.ref<i32> 14 ! CHECK-SAME: {type = private} @[[TEST6_X_PRIV:.]] : !fir.ref<i32> 19 ! CHECK-SAME: {type = firstprivate} @[[TEST6_Z_FIRSTPRIV:.]] : !fir.ref<i32> 25 ! CHECK-SAME: {type = firstprivate} @[[TEST6_Y_FIRSTPRIV:.]] : !fir.ref<i32> 31 ! CHECK-SAME: {type = firstprivate} @[[TEST6_X_FIRSTPRIV:.]] : !fir.ref<i32> 37 ! CHECK-SAME: {type = firstprivate} @[[TEST5_X_FIRSTPRIV:.]] : !fir.ref<i32> 43 ! CHECK-SAME: {type = private} @[[TEST5_X_PRIV:.]] : !fir.ref<i32> 48 ! CHECK-SAME: {type = firstprivate} @[[TEST4_Y_FIRSTPRIV:.]] : !fir.ref<i32> 54 ! CHECK-SAME: {type = firstprivate} @[[TEST4_Z_FIRSTPRIV:.]] : !fir.ref<i32> 60 ! CHECK-SAME: {type = firstprivate} @[[TEST4_X_FIRSTPRIV:.]] : !fir.ref<i3 [all...]
H A D	wsloop-reduction-mul-byref.f90	`7 ! CHECK-LABEL: omp.declare_reduction @multiply_reduction_byref_f64 : !fir.ref<f64> 9 ! CHECK: %[[REF:.]] = fir.alloca f64 10 ! CHECK: omp.yield(%[[REF]] : !fir.ref<f64>) 12 ! CHECK: ^bb0(%[[VAL_0:.]]: !fir.ref<f64>, %[[ALLOC:.]]: !fir.ref<f64>): 14 ! CHECK: fir.store %[[VAL_1]] to %[[ALLOC]] : !fir.ref<f64> 15 ! CHECK: omp.yield(%[[ALLOC]] : !fir.ref<f64>) 18 ! CHECK: ^bb0(%[[ARG0:.]]: !fir.ref<f64>, %[[ARG1:.*]]: !fir.ref<f6 [all...]`
H A D	wsloop-reduction-add-byref.f90	`4 ! CHECK-LABEL: omp.declare_reduction @add_reduction_byref_f64 : !fir.ref<f64> 6 ! CHECK: %[[REF:.]] = fir.alloca f64 7 ! CHECK: omp.yield(%[[REF:.]] : !fir.ref<f64>) 9 ! CHECK: ^bb0(%[[VAL_0:.]]: !fir.ref<f64>, %[[ALLOC:.]]: !fir.ref<f64>): 11 ! CHECK: fir.store %[[C0_1]] to %[[ALLOC]] : !fir.ref<f64> 12 ! CHECK: omp.yield(%[[ALLOC]] : !fir.ref<f64>) 15 ! CHECK: ^bb0(%[[ARG0:.]]: !fir.ref<f64>, %[[ARG1:.]]: !fir.ref<f6 [all...]`
H A D	threadprivate-use-association.f90	19 !CHECK-DAG: [[ADDR0:%.]] = fir.address_of(@blk_) : !fir.ref<!fir.array<24xi8>> 20 …G: [[NEWADDR0:%.]] = omp.threadprivate [[ADDR0]] : !fir.ref<!fir.array<24xi8>> -> !fir.ref<!fir… 21 !CHECK-DAG: [[ADDR1:%.]] = fir.address_of(@_QMtestEy) : !fir.ref<f32> 22 …hlfir.declare [[ADDR1]] {uniq_name = "_QMtestEy"} : (!fir.ref<f32>) -> (!fir.ref<f32>, !fir.ref<f3… 23 !CHECK-DAG: [[NEWADDR1:%.]] = omp.threadprivate %[[DECY]]#1 : !fir.ref<f32> -> !fir.ref<f32> 26 …DAG: [[ADDR2:%.]] = omp.threadprivate [[ADDR0]] : !fir.ref<!fir.array<24xi8>> -> !fir.ref<!fir… 27 !CHECK-DAG: [[ADDR3:%.]] = fir.convert [[ADDR2]] : (!fir.ref<!fir.array<24xi8>>) -> !fir.ref<!f… 28 …R4:%.]] = fir.coordinate_of [[ADDR3]], %{{.}} : (!fir.ref<!fir.array<?xi8>>, index) -> !fir.ref<… 29 !CHECK-DAG: [[ADDR5:%.*]] = fir.convert [[ADDR4]] : (!fir.ref<i8>) -> !fir.ref<i32> 30 …hlfir.declare [[ADDR5]] {uniq_name = "_QMtestEx"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i3… [all …]
/llvm-project/cross-project-tests/debuginfo-tests/dexter-tests/
H A D	optnone-vectors-and-functions.cpp	34 // DexLimitSteps('1', '1', from_line=ref('break_0'), to_line=ref('break_1')) 36 …alue('TypeTraits<int __attribute__((ext_vector_type(4)))>::NumElements', 4, on_line=ref('break_0')) 37 …eTraits<int __attribute__((ext_vector_type(4)))>::UnusedField', 0xdeadbeef, on_line=ref('break_0')) 38 // DexExpectWatchValue('x[0]', 1, on_line=ref('break_0')) 39 // DexExpectWatchValue('x[1]', 2, on_line=ref('break_0')) 40 // DexExpectWatchValue('x[2]', 3, on_line=ref('break_0')) 41 // DexExpectWatchValue('x[3]', 4, on_line=ref('break_0')) 42 // DexExpectWatchValue('y[0]', 5, on_line=ref('break_0')) 43 // DexExpectWatchValue('y[1]', 6, on_line=ref('break_0')) 44 // DexExpectWatchValue('y[2]', 7, on_line=ref('break_0')) [all …]
/llvm-project/llvm/test/CodeGen/Thumb2/
H A D	constant-islands.ll	`89 %ref.tmp = alloca %class.btVector3, align 4 90 %ref.tmp97 = alloca %class.btVector3, align 4 91 %ref.tmp98 = alloca float, align 4 92 %ref.tmp99 = alloca float, align 4 93 %ref.tmp100 = alloca float, align 4 94 %ref.tmp102 = alloca %class.btTransform, align 4 95 %ref.tmp107 = alloca %class.btVector3, align 4 96 %ref.tmp108 = alloca %class.btVector3, align 4 97 %ref.tmp109 = alloca float, align 4 98 %ref.tmp110 = alloca float, align 4 [all …]`

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