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/freebsd-src/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,rdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma
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H A Dmediatek,disp.txt29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
34 "mediatek,<chip>-disp-ccorr" - color correction
35 "mediatek,<chip>-disp-color" - color processor
36 "mediatek,<chip>-disp-dither" - dither
37 "mediatek,<chip>-disp-aal" - adaptive ambient light controller
38 "mediatek,<chip>-disp-gamma" - gamma correction
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H A Dmediatek,merge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Mediatek display merge, namely MERGE, is used to merge two slice-per-line
15 inputs into one side-by-side output.
24 - enum:
25 - mediatek,mt8173-disp-merge
26 - mediatek,mt8195-disp-merge
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/freebsd-src/sys/dev/bnxt/bnxt_re/
H A Dbnxt_re.h2 * Copyright (c) 2015-2024, Broadcom. All rights reserved. The term
47 #include <rdma/ib_verbs.h>
48 #include <rdma/ib_user_verbs.h>
49 #include <rdma/ib_umem.h>
50 #include <rdma/ib_addr.h>
51 #include <rdma/ib_mad.h>
52 #include <rdma/ib_cache.h>
99 * min_not_zero - return the minimum that is _not_ zero, unless both are zero
165 ((rdev)->chip_ctx->hwrm_cmd_max_timeou
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H A Dmain.c2 * Copyright (c) 2015-2024, Broadcom. All rights reserved. The term
35 #include <linux/dma-mapping.h>
40 #include <rdma/ib_user_verbs.h>
41 #include <rdma/ib_addr.h>
42 #include <rdma/ib_cache.h>
46 #include <rdma/ib_smi.h>
47 #include <rdma/ib_umem.h>
53 #include "bnxt_re-abi.h"
57 "Broadcom NetXtreme-C/E RoCE Driver " ROCE_DRV_MODULE_NAME \
63 MODULE_DESCRIPTION("Broadcom NetXtreme-
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/freebsd-src/sys/dev/ath/ath_hal/ar5210/
H A Dar5210reg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2004 Atheros Communications, Inc.
24 * Processor for IEEE 802.11a 5-GHz Wireless LANs.
72 #define AR_SLOT_TIME 0x8010 /* Length of a back-off */
92 #define AR_TRIG_LEV 0x8064 /* Minimum FIFO fill level before TX */
98 #define AR_BACKOFF 0x8088 /* Back-off status */
127 #define AR_CFG_TXFSTRT 0x00010000 /* re-enable TX DMA */
136 #define AR_ISR_RXORN_INT 0x00000020 /* RX fifo overrun */
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/freebsd-src/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gx
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H A Dmeson-g12-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-binding
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/freebsd-src/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controlle
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H A Dmt8183.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gi
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H A Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controlle
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/freebsd-src/sys/dev/cxgbe/iw_cxgbe/
H A Dt4.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
66 #define T4_PAGESIZE_MASK 0xffffffff000 /* 4KB-8TB */
72 __be32 rsvd1; /* flit 0 - hw owns */
77 u8 qp_err; /* flit 1 - sw owns */
89 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
91 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
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/freebsd-src/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 …h:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header sync …
80 …taWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo pu…
81 …x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header sync f…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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/freebsd-src/sys/contrib/device-tree/src/arm/amlogic/
H A Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpi
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/freebsd-src/sys/dev/cxgbe/common/
H A Dt4_hw.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
49 * t4_wait_op_done_val - wait until an operation is completed
52 * @mask: a single-bit field within @reg that indicates completion
61 * operation completes and -EAGAIN otherwise.
74 if (--attempts == 0) in t4_wait_op_done_val()
75 return -EAGAIN; in t4_wait_op_done_val()
89 * t4_set_reg_field - set a register field to a value
108 * t4_read_indirect - read indirectly addressed registers
123 while (nregs--) { in t4_read_indirect()
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/freebsd-src/sys/cam/scsi/
H A Dscsi_all.c1 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
78 #define ERESTART -1 /* restart syscall */
79 #define EJUSTRETURN -2 /* don't modify regs, just return */
91 * a minimum value of 100ms. Note that this is pertinent only for SPI-
142 { 0xD8, R, "CD-DA READ" }
149 * to read CD-D
5870 struct scsi_transportid_rdma *rdma; scsi_transportid_sbuf() local
6273 struct scsi_transportid_rdma *rdma; scsi_parse_transportid_rdma() local
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/freebsd-src/sys/dev/bnxt/bnxt_en/
H A Dhsi_struct_def.h1 /*-
34 * Copyright(c) 2001-2024, Broadcom. All rights reserved. The
53 /* hwrm_cmd_hdr (size:128b/16B) */
71 * * 0x0-0xFFF8 - The function ID
72 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
73 * * 0xFFFD - Reserved for user-space HWRM interface
74 * * 0xFFFF - HWRM
87 /* hwrm_resp_hdr (size:64b/8B) */
122 /* Engine CKV - The Alias key EC curve and ECC public key information. */
124 /* Engine CKV - Initialization vector. */
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/freebsd-src/sys/dev/cxgbe/
H A Dt4_main.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
272 * Each tunable is set to a default value here if it's known at compile-time.
273 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
290 int t4_ntxq = -NTXQ;
296 int t4_nrxq = -NRXQ;
302 static int t4_ntxq_vi = -NTXQ_V
9221 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; sysctl_cim_qcfg() local
9739 unsigned int size; mem_region_show() local
9893 uint32_t size = 0; sysctl_meminfo() local
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/freebsd-src/share/misc/
H A Dpci_vendors5 # Date: 2024-11-25 03:15:02
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-250
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/freebsd-src/sys/dev/bge/
H A Dif_bge.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
19 * 4. Neither the name of the author nor the names of any co-contributors
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bi
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