Searched full:pll5 (Results 1 – 12 of 12) sorted by relevance
| /freebsd-src/sys/contrib/device-tree/Bindings/clock/ |
| H A D | allwinner,sun4i-a10-pll5-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml#
23 const: allwinner,sun4i-a10-pll5-clk
47 compatible = "allwinner,sun4i-a10-pll5-clk";
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| H A D | allwinner,sun4i-a10-mbus-clk.yaml | 50 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
59 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
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| H A D | allwinner,sun4i-a10-display-clk.yaml | 53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
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| H A D | allwinner,sun4i-a10-mmc-clk.yaml | 71 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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| H A D | allwinner,sun4i-a10-mod0-clk.yaml | 67 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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| /freebsd-src/sys/contrib/device-tree/Bindings/mips/ |
| H A D | mscc.txt | 31 configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
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| /freebsd-src/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | qcom,gcc-msm8660.h | 258 #define PLL5 249 macro
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| H A D | qcom,gcc-msm8960.h | 289 #define PLL5 281 macro
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| H A D | qcom,gcc-mdm9615.h | 291 #define PLL5 281 macro
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| /freebsd-src/sys/arm/freescale/vybrid/ |
| H A D | vf_anadig.c | 67 #define ANADIG_PLL5_CTRL 0x0E0 /* PLL5 Control */
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| /freebsd-src/sys/arm/freescale/imx/ |
| H A D | imx6_ccm.c | 455 /* Set IPU1_DI0 clock to source from PLL5 and divide it by 3 */ in imx_ccm_ipu_enable()
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| /freebsd-src/sys/dev/bhnd/cores/pmu/ |
| H A D | bhnd_pmu_subr.c | 1706 * program the PLL4 and PLL5. So Skip this check for 4319. */ in bhnd_pmu1_pllinit0()
1764 /* Initialize PLL5 */ in bhnd_pmu1_pllinit0()
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