| /freebsd-src/sys/contrib/device-tree/Bindings/phy/ |
| H A D | rcar-gen2-phy.txt | 1 * Renesas R-Car generation 2 USB PHY
3 This file provides information on what the device node for the R-Car generation
4 2 USB PHY contains.
7 - compatible: "renesas,usb-phy-r8a7742" if the device is a part of R8A7742 SoC.
8 "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC.
9 "renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC.
10 "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC.
11 "renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC.
12 "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
13 "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
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| H A D | phy-hisi-inno-usb2.txt | 1 Device tree bindings for HiSilicon INNO USB2 PHY
4 - compatible: Should be one of the following strings:
5 "hisilicon,inno-usb2-phy",
6 "hisilicon,hi3798cv200-usb2-phy".
7 - reg: Should be the address space for PHY configuration register in peripheral
9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
13 - #address-cells: Must be 1.
14 - #size-cells: Must be 0.
16 The INNO USB2 PHY device should be a child node of peripheral controller that
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| H A D | marvell,armada-cp110-utmi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,armada-cp11
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| H A D | phy-bindings.txt | 1 This document explains only the device tree data binding. For general
2 information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst
4 PHY device node
8 #phy-cells: Number of cells in a PHY specifier; The meaning of all those
9 cells is defined by the binding for the phy node. The PHY
11 PHY.
14 phy-supply: Phandle to a regulator that provides power to the PHY. This
15 regulator will be managed during the PHY power on/off sequence.
19 phys: phy {
24 #phy-cells = <1>;
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| H A D | phy-da8xx-usb.txt | 1 TI DA8xx/OMAP-L1xx/AM18xx USB PHY
4 - compatible: must be "ti,da830-usb-phy".
5 - #phy-cells: must be 1.
7 This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
8 controllers on DA8xx SoCs. Consumers of this device should use index 0 for
9 the USB 2.0 phy device and index 1 for the USB 1.1 phy device.
11 It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
17 compatible = "ti,da830-cfgchip", "syscon";
21 usb_phy: usb-phy {
22 compatible = "ti,da830-usb-phy";
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| H A D | samsung-phy.txt | 2 -------------------------------------------------
5 - compatible : should be one of the listed compatibles:
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
12 - syscon - phandle to the PMU system controller
14 In case of exynos5433 compatible PHY:
15 - samsung,pmu-syscon - phandle to the PMU system controller
16 - samsung,disp-sysreg - phandle to the DISP system registers controller
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| H A D | phy-miphy365x.txt | 1 STMicroelectronics STi MIPHY365x PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
21 - #phy-cells : Should be 1 (See second example)
22 Cell after port phandle is device type from:
23 - PHY_TYPE_SATA
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| H A D | phy-miphy28lp.txt | 1 STMicroelectronics STi MIPHY28LP PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
20 Cell after port phandle is device type from:
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
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| /freebsd-src/sys/contrib/device-tree/Bindings/display/msm/ |
| H A D | dsi.txt | 5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
25 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
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| H A D | hdmi.txt | 4 - compatible: one of the following
5 * "qcom,hdmi-tx-8996"
6 * "qcom,hdmi-tx-8994"
7 * "qcom,hdmi-tx-8084"
8 * "qcom,hdmi-tx-8974"
9 * "qcom,hdmi-tx-8660"
10 * "qcom,hdmi-tx-8960"
11 - reg: Physical base address and length of the controller's registers
12 - reg-names: "core_physical"
13 - interrupts: The interrupt signal from the hdmi block.
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| /freebsd-src/sys/contrib/device-tree/Bindings/net/ |
| H A D | ibm,emac.txt | 8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
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| H A D | fsl-enetc.txt | 1 * ENETC ethernet device tree bindings
5 below device tree bindings.
9 - reg : Specifies PCIe Device Number and Function
10 Number of the ENETC endpoint device, according
12 - compatible : Should be "fsl,enetc".
14 1. The ENETC external port is connected to a MDIO configurable phy
18 In this case, the ENETC node should include a "mdio" sub-node
19 that in turn should contain the "ethernet-phy" node describing the
20 external phy. Below properties are required, their bindings
22 Documentation/devicetree/bindings/net/phy.txt.
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| H A D | cpsw.txt | 1 TI SoC Ethernet Switch Controller Device Tree Bindings
2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
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| H A D | renesas,ether.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
18 - items:
19 - enum:
20 - renesas,gether-r8a7740 # device is a part of R8A7740 SoC
21 - renesas,gether-r8a77980 # device is a part of R8A77980 SoC
22 - renesas,ether-r7s72100 # device is a part of R7S72100 SoC
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| H A D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-ma
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| H A D | apm-xgene-enet.txt | 1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
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| H A D | fsl-tsec-phy.txt | 1 * MDIO IO device
3 The MDIO is a bus to which the PHY devices are connected. For each
4 device that exists on this bus, a child node should be created. See
5 the definition of the PHY node in booting-without-of.txt for an example
6 of how to define a PHY.
9 - reg : Offset and length of the register set for the device, and optionally
10 the offset and length of the TBIPA register (TBI PHY addres
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| H A D | xilinx_axienet.txt | 1 XILINX AXI ETHERNET Device Tree Bindings
2 --------------------------------------------------------
5 provides connectivity to an external ethernet PHY supporting different
15 For more details about mdio please refer phy.txt file in the same directory.
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
25 and optionally Ethernet core. If axistream-connected is
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| H A D | qcom-emac.txt | 4 internal PHY. Each device is represented by a device tree node. A phandle
5 connects the MAC node to its corresponding internal phy node. Another
6 phandle points to the external PHY node.
11 - compatible : Should be "qcom,fsm9900-emac".
12 - reg : Offset and length of the register regions for the device
13 - interrupts : Interrupt number used by this controller
14 - mac-address : The 6-byte MAC address. If present, it is the default
16 - internal-phy : phandle to the internal PHY node
17 - phy-handle : phandle to the external PHY node
19 Internal PHY node:
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| /freebsd-src/sys/dev/isci/scil/ |
| H A D | scif_sas_smp_phy.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
74 * @brief This routine constructs a smp phy object for an expander phy and insert
75 * to owning expander device's smp_phy_list.
76 * @param[in] this_smp_phy The memory space to store a phy
77 * @param[in] owning_device The smp remote device that owns this smp phy.
78 * @param[in] expander_phy_id The expander phy id for this_smp_phy.
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| H A D | scif_sas_smp_remote_device.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 201
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| /freebsd-src/sys/contrib/device-tree/Bindings/usb/ |
| H A D | omap-usb.txt | 4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7 multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9 MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
12 interface between the controller and the phy. It should be "0" or "1"
14 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
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| H A D | msm-hsusb.txt | 6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
10 Example EHCI controller device node:
13 compatible = "qcom,ehci-host";
15 usb-phy = <&usb_otg>;
18 USB PHY with optional OTG:
21 - compatible: Should contain:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
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| /freebsd-src/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | arasan,sdhci.txt | 1 Device Tree Bindings for the Arasan SDHCI Controller
3 The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
9 [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
12 - compatible: Compatibility string. One of:
13 - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
14 - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
15 - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
16 - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
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| H A D | arasan,sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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