| /freebsd-src/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | samsung,pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylweste
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| H A D | renesas,rza1-pinctrl.txt | 5 Pin multiplexing and GPIO configuration is performed on a per-pin basis
6 writing configuration values to per-port register sets.
7 Each "port" features up to 16 pins, each of them configurable for GPIO
12 -------------------
15 - compatible: should be:
16 - "renesas,r7s72100-ports": for RZ/A1H
17 - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M
18 - "renesas,r7s72102-ports": for RZ/A1L
20 - reg
27 pinctrl: pin-controller@fcfe3000 {
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| H A D | samsung,pinctrl-pins-cfg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-pins-cfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC pin controller - pins configuration
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
18 Pins configuration for Samsung S3C/S5P/Exynos SoC pin controller.
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| H A D | marvell,dove-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4 part and usage.
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
12 Note: brackets (x) are not part of the mpp name for marvell,function and given
16 name pins functions
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
23 uart1(cts), lcd-spi(cs1), pmu*
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| H A D | samsung-pinctrl.txt | 4 controller. It controls the input/output settings on the available pads/pins
6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
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| H A D | sprd,sc9860-pinctrl.txt | 3 Please refer to sprd,pinctrl.txt in this directory for common binding part
7 - compatible: Must be "sprd,sc9860-pinctrl".
8 - reg: The register address of pin controller device.
9 - pins : An array of strings, each string containing the name of a pin.
12 - function: A string containing the name of the function, values must be
14 - drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
16 - input-schmitt-disable: Enable schmitt-trigger mode.
17 - input-schmitt-enable: Disable schmitt-trigger mode.
18 - bias-disable: Disable pin bias.
19 - bias-pull-down: Pull down on pin.
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| H A D | fsl,imx7d-pinctrl.txt | 3 iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
4 as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
5 power state retention capabilities on gpios that are part of iomuxc-lpsr
6 (GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
8 iomuxc controller for daisy chain settings, the fsl,input-sel property extends
9 fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
11 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
12 compatible = "fsl,imx7d-iomuxc-lpsr";
14 fsl,input-sel = <&iomuxc>;
18 compatible = "fsl,imx7d-iomuxc";
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| H A D | renesas,rza2-pinctrl.txt | 4 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
5 Each port features up to 8 pins, each of them configurable for GPIO
10 -------------------
13 - compatible: shall be:
14 - "renesas,r7s9210-pinctrl": for RZ/A2M
15 - reg
18 - gpio-controller
19 This pin controller also controls pins as GPIO
20 - #gpio-cells
21 Must be 2
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| H A D | fsl,imx50-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx50-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx50 datasheet for the valid pad
21 PAD_CTL_PUS_100K_UP (2 << 4)
26 PAD_CTL_DSE_HIGH (2 << 1)
31 Refer to imx50-pinfunc.h in device tree source folder for all available
|
| H A D | fsl,imx51-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx51-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx51 datasheet for the valid pad
21 PAD_CTL_PUS_100K_UP (2 << 4)
26 PAD_CTL_DSE_HIGH (2 << 1)
31 Refer to imx51-pinfunc.h in device tree source folder for all available
|
| H A D | fsl,imx53-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx53-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx53 datasheet for the valid pad
21 PAD_CTL_PUS_100K_UP (2 << 4)
26 PAD_CTL_DSE_HIGH (2 << 1)
31 Refer to imx53-pinfunc.h in device tree source folder for all available
|
| H A D | fsl,vf610-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,vf610-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is
11 such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
16 PAD_CTL_SPEED_MED (2 << 12)
24 PAD_CTL_DSE_75ohm (2 << 6)
32 PAD_CTL_PUS_100K_UP (2 << 4)
35 PAD_CTL_PUE (1 << 2)
40 Please refer to vf610-pinfunc.h in device tree source folder
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| H A D | fsl,imx6q-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6q-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx6q datasheet for the valid pad
18 PAD_CTL_PUS_100K_UP (2 << 14)
24 PAD_CTL_SPEED_MED (2 << 6)
28 PAD_CTL_DSE_120ohm (2 << 3)
37 Refer to imx6q-pinfunc.h in device tree source folder for all available
|
| H A D | fsl,imx6dl-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6dl-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx6dl datasheet for the valid pad
18 PAD_CTL_PUS_100K_UP (2 << 14)
24 PAD_CTL_SPEED_MED (2 << 6)
28 PAD_CTL_DSE_120ohm (2 << 3)
37 Refer to imx6dl-pinfunc.h in device tree source folder for all available
|
| H A D | fsl,imx35-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx35-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx35 datasheet for the valid pad
22 PAD_CTL_PUS_100K_UP (2 << 4)
28 PAD_CTL_DSE_MAX (2 << 1)
32 Refer to imx35-pinfunc.h in device tree source folder for all available
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| H A D | fsl,imx6sl-pinctrl.txt | 3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6sl-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
11 pull-up for this pin. Please refer to imx6sl datasheet for the valid pad
19 PAD_CTL_PUS_100K_UP (2 << 14)
25 PAD_CTL_SPEED_MED (2 << 6)
29 PAD_CTL_DSE_120ohm (2 << 3)
38 Refer to imx6sl-pinfunc.h in device tree source folder for all available
|
| H A D | renesas,rza1-ports.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
18 Each "port" features up to 16 pins, each of them configurable for GPIO
25 - const: renesas,r7s72100-ports # RZ/A1H
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| H A D | marvell,orion-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4 part and usage.
7 - compatible: "marvell,88f5181-pinctrl",
8 "marvell,88f5181l-pinctrl",
9 "marvell,88f5182-pinctrl",
10 "marvell,88f5281-pinctrl"
12 - reg: two register areas, the first one describing the first two
16 Available mpp pins/groups and functions:
17 Note: brackets (x) are not part of the mpp name for marvell,function and given
22 name pins functions
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| H A D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
14 Freescale IMX pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'mux' selects the function mode(also named mux
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry
41 Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
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| /freebsd-src/sys/dev/iicbus/ |
| H A D | iic_recover_bus.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
13 * 2. Redistributions in binary form must reproduce the above copyright
32 * Helper code to recover a hung i2c bus by bit-banging a recovery sequence.
35 * The most common cause is a partially-completed transaction such as rebooting
44 * embedded i2c controllers, the i2c pins can be temporarily reassigned as gpio
45 * pins to do the bus recovery, then can be assigned back to the i2c hardware.
58 iic_recover_bus(struct iicrb_pin_access *pins) in iic_recover_bus() argument
67 pins->setsda(pins->ctx, 1); in iic_recover_bus()
68 pins->setscl(pins->ctx, 1); in iic_recover_bus()
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| /freebsd-src/sys/contrib/device-tree/src/arm/microchip/ |
| H A D | lan966x-kontron-kswitch-d10-mmt.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Common part of the device tree for the Kontron KSwitch D10 MMT
6 /dts-v1/;
8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
16 stdout-path = "serial0:115200n8";
19 gpio-restart {
20 compatible = "gpio-restart";
21 pinctrl-0 = <&reset_pins>;
22 pinctrl-names = "default";
29 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
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| /freebsd-src/share/man/man4/ |
| H A D | gpioiic.4 | 9 .\" 2. Redistributions in binary form must reproduce the above copyright
30 .Nd GPIO I2C bit-banging device driver
35 .Bd -ragged -offset indent
45 .Bd -literal -offset indent
51 driver provides an IIC bit-banging interface using two GPIO pins for the
55 simulates an open collector kind of output when managing the pins on the
56 bus, even on systems which don't directly support configuring gpio pins
58 The pins are never driven to the logical value of '1'.
59 They are driven to '0' or switched to input mode (Hi-Z/tri-state), and
67 .Bl -tag -width ".Va hint.gpioiic.%d.atXXX"
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| /freebsd-src/share/man/man9/ |
| H A D | fdt_pinctrl.9 | 1 .\" -*- nroff -*-
14 .\" 2. Redistributions in binary form must reproduce the above copyright
51 As part of handling attach, it calls the
56 is used to walk the device tree and configure pins specified by the pinctrl-0
73 described by the pinctrl-N property with index
103 If the pinctrl-0 property contains references
105 their pins are configured.
107 .Bd -literal
112 uint32_t *pins, *functions;
117 npins = OF_getencprop_alloc_multi(cfgnode, "foo,pins", sizeof(*pins),
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| /freebsd-src/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | armada-xp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 #include "armada-370-xp.dtsi"
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
38 internal-regs {
40 compatible = "marvell,armada-xp-sdram-controller";
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| H A D | orion5x-maxtor-shared-storage-2.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controlle
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