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/freebsd-src/sys/contrib/device-tree/Bindings/cpufreq/
H A Dqcom-cpufreq-nvmem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
17 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
28 - qcom,apq8064
29 - qcom,apq8096
30 - qcom,ipq5332
31 - qcom,ipq6018
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/power/
H A Dqcom,rpmpd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/qcom,rpmp
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/freebsd-src/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm660.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
13 compatible = "qcom,adreno-512.0", "qcom,adreno";
14 operating-points-v2 = <&gpu_sdm660_opp_table>;
16 gpu_sdm660_opp_table: opp-table {
17 compatible = "operating-points-v2";
23 * at the same opp-level
25 opp-750000000 {
26 opp-hz = /bits/ 64 <750000000>;
27 opp-level = <RPM_SMD_LEVEL_TURBO>;
28 opp-peak-kBps = <5412000>;
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H A Dsm6350.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
8 #include <dt-bindings/clock/qcom,gcc-sm635
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H A Dsc7180.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gc
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H A Dsdm845.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-binding
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H A Dsdm670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-binding
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H A Dsm6375.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
8 #include <dt-binding
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H A Dsm8350.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interconnect/qcom,sm8350.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-binding
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H A Dsc7280.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispc
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H A Dsm8250.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm825
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H A Dipq5332.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 #include <dt-bindings/clock/qcom,apss-ipq.h>
9 #include <dt-bindings/clock/qcom,ipq533
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H A Dsc8280xp.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280x
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H A Dsc8180x.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-binding
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/freebsd-src/sys/contrib/device-tree/Bindings/opp/
H A Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
25 operating-points-v2 table when it is parsed by the OPP framework.
30 - operating-points-v2-krait-cpu
31 - operating-points-v2-kryo-cpu
[all …]
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points)
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
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H A Dopp-v2-qcom-level.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niklas Cassel <nks@flawful.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2-qcom-level
20 '^opp-?[0-9]+$':
25 opp-level: true
27 qcom,opp-fuse-level:
[all …]
H A Dopp.txt1 Generic OPP (Operating Performance Points) Bindings
2 ----------------------------------------------------
4 Devices work at voltage-current-frequency combinations and some implementations
5 have the liberty of choosing these. These combinations are called Operating
6 Performance Points aka OPPs. This document defines bindings for these OPPs
13 Binding 1: operating-points
16 This binding only supports voltage-frequency pairs.
19 - operating-points: An array of 2-tuples items, and each item consists
20 of frequency and voltage like <freq-kHz vol-uV>.
27 compatible = "arm,cortex-a9";
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H A Dqcom-nvmem-cpufreq.txt8 defines the voltage and frequency value based on the msm-id in SMEM
10 The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
13 operating-points-v2 table when it is parsed by the OPP framework.
16 --------------------
18 - operating-points-v2: Phandle to the operating-points-v2 table to use.
20 In 'operating-points-v2' table:
21 - compatible: Should be
22 - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
26 --------------------
28 - power-domains: A phandle pointing to the PM domain specifier which provides
[all …]
H A Dqcom-opp.txt3 The bindings are based on top of the operating-points-v2 bindings
4 described in Documentation/devicetree/bindings/opp/opp-v2-base.yaml
10 - compatible: Allow OPPs to express their compatibility. It should be:
11 "operating-points-v2-qcom-level"
16 - qcom,opp-fuse-level: A positive value representing the fuse corner/level
18 a certain fuse corner/level. A fuse corner/level contains e.g. ref uV,
/freebsd-src/sys/contrib/device-tree/Bindings/display/msm/
H A Dgpu.txt4 - compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or
5 "amd,imageon-XYZ.W", "amd,imageon"
6 for example: "qcom,adreno-306.0", "qcom,adreno"
7 Note that you need to list the less specific "qcom,adreno" (since this
9 with the chip-id.
10 If "amd,imageon" is used, there should be no top level msm device.
11 - reg: Physical base address and length of the controller's registers.
12 - interrupts: The interrupt signal from the gpu.
13 - clocks: device clocks (if applicable)
14 See ../clocks/clock-bindings.txt for details.
[all …]
H A Dgpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schema
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/freebsd-src/sys/contrib/device-tree/Bindings/power/avs/
H A Dqcom,cpr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/avs/qcom,cpr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niklas Cassel <nks@flawful.org>
23 - enum:
24 - qcom,qcs404-cpr
25 - const: qcom,cpr
36 - description: Reference clock.
38 clock-names:
[all …]
H A Dqcom,cpr.txt1 QCOM CPR (Core Power Reduction)
10 - compatible:
13 Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404
15 - reg:
17 Value type: <prop-encoded-array>
20 - interrupts:
22 Value type: <prop-encoded-array>
25 - clocks:
27 Value type: <prop-encoded-array>
30 - clock-names:
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/interconnect/
H A Dqcom,msm8998-bwmon.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,msm899
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