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/freebsd-src/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A Dextended.json6 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
12 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
18 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour…
24 … "A directory write to the Level-1 Instruction cache directory where the returned cache line was s…
30 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour…
36 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
42 …"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line w…
48 …"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache…
53 "BriefDescription": "L1D Read-only Exclusive Writes",
54 …PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a R…
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/s390/cf_z14/
H A Dextended.json5 "BriefDescription": "L1D Read-only Exclusive Writes",
6 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
18 …data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this …
23 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
24 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
29 "BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
30 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"
36 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour…
48 …tion cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache i…
54 … "A directory write to the Level-1 Instruction cache directory where the returned cache line was s…
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/s390/cf_z13/
H A Dextended.json5 "BriefDescription": "L1D Read-only Exclusive Writes",
6 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
12 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
18 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
23 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
24 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a on…
29 "BriefDescription": "DTLB1 Two-Gigabyte Page Writes",
30 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a tw…
36 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour…
42 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/s390/cf_z196/
H A Dextended.json6 …ion": "A directory write to the Level-1 D-Cache directory where the returned cache line was source…
12 …ion": "A directory write to the Level-1 I-Cache directory where the returned cache line was source…
18 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
30 "PublicDescription": "Incremented by one for every store sent to Level-2 cache"
35 "BriefDescription": "L1D Off-Book L3 Sourced Writes",
36 …: "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced fr…
41 "BriefDescription": "L1D On-Book L4 Sourced Writes",
42 …": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced f…
47 "BriefDescription": "L1I On-Book L4 Sourced Writes",
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dgpmc-eth.txt1 Device tree bindings for Ethernet chip connected to TI GPMC
4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28 - compatible: Compatible string property for the ethernet child device.
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/mtd/
H A Dgpmc-nor.txt8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 - bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
12 16-bit devices and so must be either 1 or 2 bytes.
13 - compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
14 - gpmc,cs-on-ns: Chip-select assertion time
15 - gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
16 - gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
17 - gpmc,oe-on-ns: Output-enable assertion time
18 - gpmc,oe-off-ns: Output-enable de-assertion time
19 - gpmc,we-on-ns Write-enable assertion time
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
15 represents any device connected to the GPMC bus. It may be a Flash chip,
16 RAM chip or Ethernet controller, etc. These properties are meant for
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
[all …]
H A Domap-gpmc.txt7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
[all …]
H A Dmvebu-devbus.txt9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
16 This is the base address of a chip select within
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
[all …]
/freebsd-src/share/man/man4/
H A Dacpi_hp.435 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
48 driver provides support for ACPI-controlled features found on HP laptops
63 .Bl -tag -width "subsystem" -offset indent -compact
77 .Bl -tag -width "0xc0" -offset indent -compact
99 .Bl -tag -width indent
101 Toggle WLAN chip activity.
103 (read-only)
106 (read-only)
107 WLAN on air (chip enabled, hardware switch enabled + enabled in BIOS)
[all …]
H A Dle.43 .\"-
8 .\" at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
47 .Bd -ragged -offset indent
54 .Bd -literal -offset indent
58 For ISA non-PnP adapters, the port address as well as the IRQ and the DRQ
78 .Pq CMOS, pin-compatible
91 family of chips, which are single-chip implementations of a
93 chip and a DMA engine.
99 .Tn AMD Am79C970 PCnet-PCI
101 .Tn AMD Am79C971 PCnet-FAST
[all …]
/freebsd-src/sys/dev/usb/video/
H A Dudl.c3 /*-
21 * Driver for the "DisplayLink DL-120 / DL-160" graphic chips based on
77 &udl_fps, 0, "Frames Per Second, 1-60");
199 if (buf->size == size) { in udl_buffer_alloc()
206 uint8_t *ptr = ((uint8_t *)buf) - size; in udl_buffer_alloc()
232 buf->size = size; in udl_buffer_free()
240 unsigned i = sc->sc_cur_mode; in udl_get_fb_size()
249 unsigned i = sc->sc_cur_mode; in udl_get_fb_width()
257 unsigned i = sc->sc_cur_mod in udl_get_fb_height()
744 udl_lookup_mode(uint16_t hdisplay,uint16_t vdisplay,uint8_t hz,uint16_t chip,uint32_t clock) udl_lookup_mode() argument
1113 udl_cmd_write_buf_le16(struct udl_softc * sc,const uint8_t * buf,uint32_t off,uint8_t pixels,int flags) udl_cmd_write_buf_le16() argument
[all...]
/freebsd-src/sys/dev/iicbus/pmic/rockchip/
H A Drk8xx.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2018-2021 Emmanuel Vadot <manu@FreeBSD.org>
82 if (bootverbose && sc->type == RK805) { in rk8xx_start()
85 device_printf(dev, "Cannot read chip name reg\n"); in rk8xx_start()
90 device_printf(dev, "Cannot read chip version reg\n"); in rk8xx_start()
93 device_printf(dev, "Chip Name: %x\n", in rk8xx_start()
95 device_printf(dev, "Chip Version: %x\n", data[1] & 0xf); in rk8xx_start()
101 config_intrhook_disestablish(&sc->intr_hook); in rk8xx_start()
114 device_printf(sc->dev, "Powering off...\n"); in rk8xx_poweroff()
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/net/wireless/
H A Dti,wl1251.txt3 The wl1251 chip can be connected via SPI or via SDIO. This
4 document describes the binding for the SPI connected chip.
7 - compatible : Should be "ti,wl1251"
8 - reg : Chip select address of device
9 - spi-max-frequency : Maximum SPI clocking speed of device in Hz
10 - interrupts : Should contain interrupt line
11 - vio-supply : phandle to regulator providing VIO
14 - ti,wl1251-has-eeprom : boolean, the wl1251 has an eeprom connected, which
16 - ti,power-gpio : GPIO connected to chip's PMEN pin if operated in
18 - Please consult Documentation/devicetree/bindings/spi/spi-bus.txt
[all …]
/freebsd-src/sys/dev/usb/net/
H A Dif_smsc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 * Microchip LAN9xxx devices (https://www.microchip.com/en-us/product/lan9500a)
33 * The LAN9500 & LAN9500A devices are stand-alone USB to Ethernet chips that
47 * ---------------------------------
48 * The chip supports both tx and rx offloading of UDP & TCP checksums, this
52 * the Ethernet frame, this means if the frame is padded with non-zero values
167 device_printf((sc)->sc_ue.ue_dev, "debug: " fmt, ##args); \
174 device_printf((sc)->sc_ue.ue_dev, "warning: " fmt, ##args)
177 device_printf((sc)->sc_ue.ue_dev, "error: " fmt, ##args)
[all …]
H A Dif_muge.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
34 * USB-To-Ethernet adapter driver for Microchip's LAN78XX and related families.
42 * USB 2 to 10/100/1000 Mbps Ethernet with built-in USB hub
45 * This driver is based on the if_smsc driver, with lan78xx-specific
49 * ------------------
53 * - TX checksum offloading: Nothing has been implemented yet.
54 * - Direct address translation filtering: Implemented but untested.
55 * - VLAN tag removal.
56 * - Support for USB interrupt endpoints.
[all …]
/freebsd-src/sys/dev/rtwn/rtl8192c/
H A Dr92c_init.c3 /*-
6 * Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org>
57 struct r92c_softc *rs = sc->sc_priv; in r92c_check_condition()
65 "%s: condition byte 0: %02X; chip %02X, board %02X\n", in r92c_check_condition()
66 __func__, cond[0], rs->chip, rs->board_type); in r92c_check_condition()
68 if (!(rs->chip & R92C_CHIP_92C)) { in r92c_check_condition()
69 if (rs->board_type == R92C_BOARD_TYPE_HIGHPA) in r92c_check_condition()
71 else if (rs->board_type == R92C_BOARD_TYPE_MINICARD) in r92c_check_condition()
76 if (rs->board_type == R92C_BOARD_TYPE_MINICARD) in r92c_check_condition()
95 for (i = 0; i < sc->page_count; i++) { in r92c_llt_init()
[all …]
/freebsd-src/sys/arm/freescale/
H A Dfsl_ocotp.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 * Access to the Freescale i.MX6 On-Chip One-Time-Programmable Memory
73 if ((root = OF_finddevice("/")) == -1) in fsl_ocotp_devmap()
75 if ((child = fdt_depth_search_compatible(root, "fsl,imx6q-ocotp", 0)) == 0) in fsl_ocotp_devmap()
99 RD4(struct ocotp_softc *sc, bus_size_t off) in RD4() argument
102 return (bus_read_4(sc->mem_res, off)); in RD4()
120 sc->dev = dev; in ocotp_attach()
124 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in ocotp_attach()
126 if (sc->mem_res == NULL) { in ocotp_attach()
[all …]
/freebsd-src/sys/dev/iicbus/rtc/
H A Dnxprtc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * Driver for NXP real-time clock/calendar chips:
31 * - PCF8563 = low power, countdown timer
32 * - PCA8565 = like PCF8563, automotive temperature range
33 * - PCF8523 = low power, countdown timer, oscillator freq tuning, 2 timers
34 * - PCF2127 = like PCF8523, industrial, tcxo, tamper/ts, i2c & spi, 512B ram
35 * - PCA2129 = like PCF8523, automotive, tcxo, tamper/ts, i2c & spi, (note 1)
36 * - PCF2129 = like PCF8523, industrial, tcxo, tamper/ts, i2c & spi, (note 1)
83 * Registers, bits within them, and masks that are common to all chip types.
[all …]
/freebsd-src/sys/dev/ath/ath_hal/ar5212/
H A Dar5212_power.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
29 * Notify Power Mgt is enabled in self-generated frames.
30 * If requested, force chip awake.
32 * Returns A_OK if chip is awake or successfully forced awake.
35 * There is a problem with the chip where sometimes it will not wake up.
50 * with the chip powered down the read returns 0xffffffff in ar5212SetPowerModeAwake()
54 * ANI is in operation as no one knows to turn off the MIB in ar5212SetPowerModeAwake()
[all …]
/freebsd-src/sys/contrib/dev/rtw88/
H A Dcoex.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
16 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_next_rssi_state() local
17 u8 tol = chip in rtw_coex_next_rssi_state()
39 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_limited_tx() local
368 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_write_scbd() local
403 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_read_scbd() local
413 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_check_rfk() local
492 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_monitor_bt_enable() local
527 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_update_wl_link_info() local
708 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_update_bt_link_info() local
808 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_update_wl_ch_info() local
935 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_coex_ctrl_owner() local
983 const struct rtw_chip_info *chip = rtwdev->chip; rtw_btc_wltoggle_table_a() local
1067 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_table() local
1137 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_set_tdma() local
1195 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_tdma() local
1528 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_coex_all_off() local
1551 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_freerun() local
1596 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_rf4ce() local
1621 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_bt_whql_test() local
1646 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_bt_relink() local
1686 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_bt_idle() local
1755 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_bt_inquiry() local
1855 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_bt_game_hid() local
1903 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_bt_hfp() local
1934 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_bt_hid() local
2017 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_bt_a2dp() local
2059 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_bt_a2dpsink() local
2098 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_bt_pan() local
2135 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_bt_a2dp_hid() local
2192 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_bt_a2dp_pan() local
2249 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_bt_pan_hid() local
2284 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_bt_a2dp_pan_hid() local
2318 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_wl_under5g() local
2350 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_wl_only() local
2374 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_wl_native_lps() local
2413 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_wl_linkscan() local
2453 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_action_wl_not_connected() local
2530 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_run_coex() local
3004 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_bt_info_notify() local
3272 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_bt_hid_info_notify() local
3362 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_query_bt_hid_list() local
3584 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_get_table_index() local
3620 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_get_tdma_index() local
3738 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_set_coexinfo_hw() local
3912 const struct rtw_chip_info *chip = rtwdev->chip; rtw_coex_display_coex_info() local
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/mfd/
H A Dtwl4030-power.txt8 - compatible : must be one of the following
9 "ti,twl4030-power"
10 "ti,twl4030-power-reset"
11 "ti,twl4030-power-idle"
12 "ti,twl4030-power-idle-osc-off"
14 The use of ti,twl4030-power-reset is recommended at least on
17 When using ti,twl4030-power-idle, the TI recommended configuration
20 When using ti,twl4030-power-idle-osc-off, the TI recommended
22 down during off-idle. Note that this does not work on all boards
27 - ti,system-power-controller: This indicates that TWL4030 is the
[all …]
H A Dsprd,sc27xx-pmic.txt6 interface support function in a single chip. It has 6 major functional
8 - DCDCs to support CPU, memory.
9 - LDOs to support both internal and external requirement.
10 - Battery management system, such as charger, fuel gauge.
11 - Audio codec.
12 - User interface function, such as indicator, flash LED and so on.
13 - IC level interface, such as power on/off control, RTC and typec and so on.
16 - compatible: Should be one of the following:
22 - reg: The address of the device chip select, should be 0.
23 - spi-max-frequency: Typically set to 26000000.
[all …]
/freebsd-src/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
[all …]
/freebsd-src/sys/dev/ntb/ntb_hw/
H A Dntb_hw_plx.c1 /*-
2 * Copyright (c) 2017-2019 Alexander Motin <mav@FreeBSD.org>
28 * The Non-Transparent Bridge (NTB) is a device that allows you to connect
29 * two or more systems using a PCI-e links, providing remote memory access.
83 u_int ntx; /* NTx number within chip. */
85 u_int port; /* Port number within chip. */
86 u_int alut; /* A-LUT is enabled for NTx */
110 #define PLX_NTX_BASE(sc) ((sc)->ntx ? PLX_NT1_BASE : PLX_NT0_BASE)
115 (PLX_NTX_BASE(sc) + ((sc)->link ? PLX_NTX_LINK_OFFSET : 0))
117 (PLX_NTX_BASE(sc) + ((sc)->link ? 0 : PLX_NTX_LINK_OFFSET))
[all …]

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