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/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXReplaceImageHandles.cpp1 //===-- NVPTXReplaceImageHandles.cpp - Replace image handles for Fermi ----===//
5 // SPDX-License-Identifier: Apache-2.
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H A DNVPTXISelDAGToDAG.cpp1 //===-- NVPTXISelDAGToDAG.cpp - A dag to dag inst selector for NVPTX ------
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H A DNVPTXInstrInfo.cpp1 //===- NVPTXInstrInfo.cpp - NVPTX Instruction Information -------
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H A DNVPTXRegisterInfo.cpp1 //===- NVPTXRegisterInfo.cpp - NVPTX Register Information -------
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H A DNVPTXProxyRegErasure.cpp1 //===- NVPTXProxyRegErasure.cpp - NVPTX Proxy Register Instruction Erasure -==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===--
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H A DNVPTXPeephole.cpp1 //===-- NVPTXPeephole.cpp - NVPTX Peephole Optimiztions -------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // In NVPTX, NVPTXFrameLowering will emit following instruction at the beginning
32 //===----------------------------------------------------------------------===//
34 #include "NVPTX.h"
45 #define DEBUG_TYPE "nvptx-peephole"
62 return "NVPTX optimize redundant cvta.to.local instruction"; in getPassName()
73 INITIALIZE_PASS(NVPTXPeephole, "nvptx-peephole", "NVPTX Peephole", false, false)
79 if (Root.getOpcode() != NVPTX::cvta_to_local_64 && in isCVTAToLocalCombinationCandidate()
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H A DNVPTXFrameLowering.cpp1 //=======- NVPTXFrameLowering.cpp - NVPTX Frame Information ---*- C++ -*-=====//
5 // SPDX-Licens
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/llvm-project/llvm/test/Transforms/OpenMP/
H A Dcustom_state_machines.ll1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -
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H A Dspmdization.ll1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
2 ; RUN: opt --mtriple=amdgcn-amd-amdhs
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H A Dspmdization_indirect.ll1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
2 ; RUN: opt --mtriple=amdgcn-amd-amdhs
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/llvm-project/clang/test/Headers/
H A Dopenmp_new_nothrow.cpp1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2 …-std=c++03 -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_f…
3 …-std=c++11 -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_f…
5 …-std=c++03 -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_f…
6 …-std=c++11 -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_f…
9 // expected-no-diagnostics
16 // NVPTX-LABEL: define hidden noundef ptr @_Z17new_stuff_nothrowv
17 // NVPTX-SAME: () #[[ATTR0:[0-9]+]] {
18 // NVPTX-NEXT: entry:
19 …NVPTX-NEXT: [[CALL:%.*]] = call noalias noundef ptr @_ZnwmRKSt9nothrow_t(i64 noundef 4, ptr nou…
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/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXInstPrinter.cpp1 //===-- NVPTXInstPrinter.cpp - PTX assembly instruction printing -------
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/llvm-project/llvm/test/CodeGen/NVPTX/
H A Dsm-version.ll1 ; RUN: llc < %s -mtriple=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=SM20
2 ; RUN: llc < %s -mtriple=nvptx -mcpu=sm_21 | FileCheck %s -
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H A Dfma-disable.ll1 ; RUN: llc < %s -mtriple=nvptx -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
2 ; RUN: llc < %s -mtripl
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H A Dlower-ctor-dtor.ll1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals --include-generated-funcs --version 3
2 ; RUN: opt -
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/llvm-project/clang/test/Driver/
H A Dnvptx-cuda-system-arch.c2 // XFAIL: target={{.*}}-zos{{.*}}
4 // RUN: mkdir -p %t
5 // RUN: cp %S/Inputs/nvptx-arch/nvptx_arch_fail %t/
6 // RUN: cp %S/Inputs/nvptx-arch/nvptx_arch_sm_70 %t/
7 // RUN: cp %S/Inputs/nvptx-arch/nvptx_arch_sm_89_sm_80 %t/
14 // case when nvptx-arc
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H A Dopenmp-system-arch.c2 // XFAIL: target={{.*}}-zos{{.*}}
4 // RUN: mkdir -p %t
5 // RUN: cp %S/Inputs/amdgpu-arch/amdgpu_arch_fail %t/
6 // RUN: cp %S/Inputs/amdgpu-arch/amdgpu_arch_gfx906 %t/
7 // RUN: cp %S/Inputs/nvptx-arch/nvptx_arch_fail %t/
8 // RUN: cp %S/Inputs/nvptx-arch/nvptx_arch_sm_70 %t/
18 // case when nvptx-arc
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/llvm-project/clang/test/OpenMP/
H A Dnvptx_asm_delayed_diags.c1 …N: %clang_cc1 -fopenmp -fopenmp-version=45 -x c -triple i386-unknown-unknown -fopenmp-targets=nvpt…
2 …-verify -fopenmp -fopenmp-version=45 -x c -triple nvptx-unknown-unknown -aux-triple i386-unknown-u…
3 …-verify -DDIAGS -DIMMEDIATE -fopenmp -fopenmp-version=45 -x c -triple nvptx-unknown-unknown -aux-t…
4 …-verify -DDIAGS -DDELAYED -fopenmp -fopenmp-version=45 -x c -triple nvptx-unknown-unknown -aux-tri…
5 // RUN: %clang_cc1 -fopenmp -x c -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -e…
6 …-verify=expected,omp5 -fopenmp -x c -triple nvptx-unknown-unknown -aux-triple i386-unknown-unknown…
7 …-verify=expected,omp5 -DDIAGS -DOMP5 -DIMMEDIATE -fopenmp -x c -triple nvptx-unknown-unknown -aux-…
8 …-verify=expected,omp5 -DDIAGS -DOMP5 -DDELAYED -fopenmp -x c -triple nvptx-unknown-unknown -aux-tr…
9 // REQUIRES: x86-registered-target
10 // REQUIRES: nvptx-registered-target
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H A Dnvptx_va_arg_delayed_diags.c1 // RUN: %clang_cc1 -fopenmp -x c -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -e…
2 …-verify -fopenmp -x c -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda %s -fopenmp…
3 …-verify -DDIAGS -DIMMEDIATE -fopenmp -x c -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvi…
4 …-verify -DDIAGS -DDELAYED -fopenmp -x c -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidi…
5 // REQUIRES: x86-registered-target
6 // REQUIRES: nvptx-registered-target
9 // expected-no-diagnostics
14 // expected-error@+4 {{CUDA device code does not support va_arg}} in foo()
30 // expected-error@+4 {{CUDA device code does not support va_arg}} in t1()
48 // expected-note@+2 {{called by 'main'}} in main()
/llvm-project/clang/test/CodeGen/
H A Dnvptx-cpus.c1 // RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_20 -O3 -o %t %s -emit-llvm
2 // RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_21 -O3 -o %t %s -emit-llvm
3 // RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_30 -O3 -o %t %s -emit-llvm
4 // RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_35 -O3 -o %t %s -emit-llvm
5 // RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_37 -O3 -o %t %s -emit-llvm
6 // RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_50 -O3 -o %t %s -emit-llvm
7 // RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_52 -O3 -o %t %s -emit-llvm
8 // RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_53 -O3 -o %t %s -emit-llvm
/llvm-project/clang/test/CodeGenCUDA/
H A Ddevice-var-init.cu1 // REQUIRES: nvptx-registered-target
2 // REQUIRES: amdgpu-registered-target
7 // RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -fcuda-i
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H A Dlink-device-bitcode.cu2 // http://llvm.org/docs/NVPTXUsage.html#linking-with-libdevice
4 // REQUIRES: nvptx-registered-target
7 // RUN: %clang_cc1 -triple nvptx-unknown-cuda -emit-llvm-bc \
8 // RUN: -disable-llvm-passes -o %t.bc %S/Inputs/device-code.ll
9 // RUN: %clang_cc1 -triple nvptx-unknown-cuda -emit-llvm-bc \
10 // RUN: -disable-llvm-passes -o %t-2.bc %S/Inputs/device-code-2.ll
12 // Make sure function in device-code gets linked in and internalized.
13 // RUN: %clang_cc1 -triple nvptx-unknown-cuda -fcuda-is-device \
14 // RUN: -mlink-builtin-bitcode %t.bc -emit-llvm \
15 // RUN: -disable-llvm-passes -o - %s \
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/llvm-project/libc/utils/gpu/loader/
H A DCMakeLists.txt11 target_compile_options(gpu_loader PUBLIC -fno-rtti)
14 find_package(hsa-runtime64 QUIET 1.2.0 HINTS ${CMAKE_INSTALL_PREFIX} PATHS /opt/rocm)
15 if(hsa-runtime64_FOUND)
22 add_subdirectory(nvptx)
25 if(TARGET amdhsa-loader AND LIBC_TARGET_ARCHITECTURE_IS_AMDGPU)
27 add_dependencies(libc.utils.gpu.loader amdhsa-loader)
31 TARGET amdhsa-loader
32 EXECUTABLE "$<TARGET_FILE:amdhsa-loader>"
34 elseif(TARGET nvptx
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/llvm-project/libc/docs/gpu/
H A Dusing.rst27 ----------
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/llvm-project/clang/lib/Sema/
H A DSemaNVPTX.cpp1 //===------ SemaNVPTX.cpp ------- NVPTX target-specific routines ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements semantic analysis functions specific to NVPTX.
11 //===----------------------------------------------------------------------===//
25 case NVPTX::BI__nvvm_cp_async_ca_shared_global_4: in CheckNVPTXBuiltinFunctionCall()
26 case NVPTX::BI__nvvm_cp_async_ca_shared_global_8: in CheckNVPTXBuiltinFunctionCall()
27 case NVPTX::BI__nvvm_cp_async_ca_shared_global_16: in CheckNVPTXBuiltinFunctionCall()
28 case NVPTX::BI__nvvm_cp_async_cg_shared_global_16: in CheckNVPTXBuiltinFunctionCall()

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