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/freebsd-src/sys/contrib/device-tree/Bindings/soc/mediatek/
H A Dmediatek,mutex.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex
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/freebsd-src/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,disp.txt4 The Mediatek display subsystem consists of various DISP function blocks in the
10 All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
14 DISP function blocks
19 interface, or writes pixels back to memory. All DISP function blocks have
29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
34 "mediatek,<chip>-disp-ccorr" - color correction
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H A Dmediatek,mutex.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek mutex
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Mediatek mutex, namely MUTEX, is used to send the triggers signals called
15 Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
17 In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
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/freebsd-src/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt6795.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
12 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
13 #include <dt-bindings/memory/mt6795-larb-port.h>
14 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
15 #include <dt-bindings/power/mt6795-power.h>
16 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
20 interrupt-parent = <&sysirq>;
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H A Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-binding
1270 mutex: mutex@14020000 { global() label
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H A Dmt8186.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-binding
1724 mutex: mutex@14001000 { global() label
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H A Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controlle
3228 mutex: mutex@1c016000 { global() label
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H A Dmt8183.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gi
1831 mutex: mutex@14016000 { global() label
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H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controlle
1454 mutex: mutex@14001000 { global() label
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/freebsd-src/sys/contrib/device-tree/Bindings/mailbox/
H A Dmtk-gce.txt9 mailbox.txt for generic information about mailbox device-tree bindings.
12 - compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce",
13 "mediatek,mt8186-gce", "mediatek,mt8192-gce", "mediatek,mt8195-gce" or
14 "mediatek,mt6779-gce".
15 - reg: Address range of the GCE unit
16 - interrupts: The interrupt signal from the GCE block
17 - clock: Clocks according to the common clock binding
18 - clock-names: Must be "gce" to stand for GCE clock
19 - #mbox-cells: Should be 2.
26 - mboxes: Client use mailbox to communicate with GCE, it should have this
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/freebsd-src/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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