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/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schema
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H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
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H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
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H A Dingenic,mac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ingenic,mac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MAC in Ingenic SoCs
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac
20 - ingenic,x1600-mac
21 - ingenic,x1830-mac
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H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
23 transformer. This device interfaces directly to the MAC layer through the
34 nvmem-cells:
40 nvmem-cell-names:
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H A Dmediatek-dwmac.txt9 - compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC
10 - reg: Address and length of the register set for the device
11 - interrupts: Should contain the MAC interrupts
12 - interrupt-names: Should contain a list of interrupt names corresponding to
14 Should be "macirq" for the main MAC IRQ
15 - clocks: Must contain a phandle for each entry in clock-names.
16 - clock-names: The name of the clock listed in the clocks property. These are
18 - mac-address: See ethernet.txt in the same directory
19 - phy-mode: See ethernet.txt in the same directory
20 - mediatek,pericfg: A phandle to the syscon node that control ethernet
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H A Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwma
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H A Dloongson,ls1b-gmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/loongson,ls1b-gmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1B Gigabit Ethernet MAC Controller
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 Loongson-1B Gigabit Ethernet MAC Controller is based on
14 Synopsys DesignWare MAC (version 3.50a).
17 - Dual 10/100/1000Mbps GMAC controllers
18 - Full-duplex operation (IEEE 802.3x flow control automatic transmission)
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H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare MAC
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giusepp
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H A Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd-src/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
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/freebsd-src/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controlle
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/freebsd-src/sys/contrib/device-tree/Bindings/firmware/
H A Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
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/freebsd-src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mn.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-binding
637 clk: clock-controller@30380000 { global() label
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H A Dimx8mp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-binding
727 clk: clock-controller@30380000 { global() label
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H A Dimx8mm.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gi
636 clk: clock-controller@30380000 { global() label
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H A Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-rese
848 clk: clock-controller@30380000 { global() label
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/freebsd-src/sys/dev/ath/ath_hal/ar5210/
H A Dar5210reg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2004 Atheros Communications, Inc.
23 * Register defintions for the Atheros AR5210/5110 MAC/Basedband
24 * Processor for IEEE 802.11a 5-GHz Wireless LANs.
37 #define AR_RXDP 0x000c /* RX queue descriptor ptr register */
45 #define AR_RXCFG 0x0034 /* RX configuration register */
48 #define AR_RXNOFRM 0x0048 /* RX no frame timeout register */
50 #define AR_RPGTO 0x0050 /* RX frame gap timeout register */
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/freebsd-src/sys/dev/cxgb/common/
H A Dcxgb_vsc7323.c2 SPDX-License-Identifier: BSD-2-Clause
54 const struct mdio_ops *mo = adapter_info(adap)->mdio_ops; in t3_elmr_blk_write()
57 ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_ADDR, start); in t3_elmr_blk_write()
58 for ( ; !ret && n; n--, vals++) { in t3_elmr_blk_write()
59 ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_LO, in t3_elmr_blk_write()
62 ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_HI, in t3_elmr_blk_write()
78 const struct mdio_ops *mo = adapter_info(adap)->mdio_ops; in t3_elmr_blk_read()
82 ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_ADDR, start); in t3_elmr_blk_read()
87 ret = mo->read(adap, ELMR_MDIO_ADDR, 0, ELMR_STAT, &v); in t3_elmr_blk_read()
95 ret = -ETIMEDOUT; in t3_elmr_blk_read()
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/freebsd-src/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controlle
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/freebsd-src/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-binding
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/freebsd-src/sys/dev/etherswitch/ar40xx/
H A Dar40xx_hw_port.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
54 #include <dev/clk/clk.h>
95 * The ar40xx code in linux/u-boot instead has a whole workaround in ar40xx_hw_port_init()
97 * NOTABLY - they do NOT enable the TX/RX MAC here or autoneg - in ar40xx_hw_port_init()
100 * SO - for now the port is left off until the PHY state changes. in ar40xx_hw_port_init()
126 * Call when the link for a non-CPU port is down.
128 * This will turn off the MAC/forwarding path for this port.
143 * Call when the link for a non-CPU port is up.
145 * This will turn on the default auto-link checking and
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/freebsd-src/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_mac_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
41 * @brief Ethernet MAC registers
307 struct al_eth_mac_10g_stats_v3_rx rx; member
388 /* [0xc] MAC selection configuration */
390 /* [0x10] 10/100/1000 MAC external configuration */
392 /* [0x14] 10/100/1000 MAC status */
398 /* [0x20] 1/2.5/10G MAC external configuration */
400 /* [0x24] 1/2.5/10G MAC status */
482 /* [0x4] EEE, number of times the MAC went into low power mode */
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/freebsd-src/sys/contrib/device-tree/src/arm/nxp/ls/
H A Dls1021a-tqmls1021a-mbls1021a.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
5 * D-82229 Seefeld, Germany.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/linux-event-codes.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/leds/leds-pca9532.h>
15 #include <dt-bindings/net/ti-dp83867.h>
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/freebsd-src/sys/contrib/device-tree/src/arm/st/
H A Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cell
729 mac: ethernet@40028000 { global() label
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