lo\-x2\-en (full) in projects: freebsd-src

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Searched +full:lo +full:- +full:x2 +full:- +full:en (Results 1 – 20 of 20) sorted by relevance

/freebsd-src/sys/contrib/device-tree/Bindings/iio/frequency/
H A D	adi,adrf6780.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Antoniu Miclaus <antoniu.miclaus@analog.com> 16 https://www.analog.com/en/products/adrf6780.html 21 - adi,adrf6780 26 spi-max-frequency: 34 clock-names: 36 - const: lo_in 38 clock-output-names: [all …]`
/freebsd-src/sys/crypto/openssl/aarch64/
H A D	aesv8-armx.S	`1 /* Do not modify. This file is auto-generated from aesv8-armx.pl. */ 5 .arch armv8-a+crypto 10 .long 0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d // rotate-n-splat 19 // Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later. 20 stp x29,x30,[sp,#-16]! 22 mov x3,#-1 25 cmp x2,#0 27 mov x3,#-2 51 st1 {v3.4s},[x2],#16 69 st1 {v3.4s},[x2],#16 [all …]`
/freebsd-src/crypto/openssl/crypto/aes/asm/
H A D	aesv8-armx.pl	2 # Copyright 2014-2023 The OpenSSL Project Authors. All Rights Reserved. 18 # module is endian-agnostic in sense that it supports both big- and 19 # little-endian cases. As does it support both 32- and 64-bit modes 24 # instruction latencies and issue rates. On Cortex-A53, an in-order 25 # execution core, this costs up to 10-15%, which is partially 26 # compensated by implementing dedicated code path for 128-bit 27 # CBC encrypt case. On Cortex-A57 parallelizable mode performance 32 # Key to performance of parallelize-able modes is round instruction 42 # Performance in cycles per byte processed with 128-bit key: 46 # Cortex-A53 1.32 1.17/1.29(**) 1.36/1.46 [all …]
/freebsd-src/share/doc/smm/18.net/
H A D	6.t	90 be described in detail later. A pointer to a protocol-specific 125 #define SS_NBIO 0x100 /* non-blocking ops / 136 set with \fIfcntl\fP. ``Non-blocking'' I/O implies that 151 super-user. Only privileged sockets may 184 (assuming non-blocking I/O has not been specified). 186 * The low-water mark is always presumed to be 0 205 Stream-oriented sockets queue data with no addresses, headers 210 Record-oriented sockets, including datagram sockets, 289 socket-visible characteristics, some of which are used in 301 /* protocol-protocol hooks */ [all …]
/freebsd-src/sys/dev/ixgbe/
H A D	ixgbe_type.h	`2 SPDX-License-Identifier: BSD-3-Clause 4 Copyright (c) 2001-2020, Intel Corporation 42 * - IXGBE_ERROR_INVALID_STATE 48 * - IXGBE_ERROR_POLLING 53 * - IXGBE_ERROR_CAUTION 58 * - IXGBE_ERROR_SOFTWARE 64 * - IXGBE_ERROR_ARGUMEN [all...]`
/freebsd-src/contrib/file/magic/Magdir/
H A D	images	`2 #---------- [all...]`
/freebsd-src/contrib/libpcap/
H A D	CHANGES	`5 Mark pcap_vasprintf() as printf-like. 16 Avoid casting hack for the Windows cleanup-on-exit routine. 21 Remove the unused pcap-rpcap-int.h header file. 23 Make some static variables thread-local; fixes issue #1174. 36 Avoid 32-bit unsigned integer overflow in USB captures. Fixes 49 Report {non-existent zone}/{interface} errors appropriately. 50 Allow attaching to links owned by a non-global zone. (Based on 55 in recent SDKs, including tagging pcap-named [all...]`
/freebsd-src/sys/contrib/dev/rtw89/
H A D	coex.c	`1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 33 CXTDMA_AUTO = 0x2, 41 CXFLC_QOSNULL = 0x2, 213 #define RTW89_DEFAULT_BTC_VER_IDX (ARRAY_SIZE(rtw89_btc_ver_defs) - 1) 330 CXPOLICY_TYPE = 0x2, 2280 u8 en = 0, i, ch = 0, bw = 0; _set_bt_afh_info() local [all...]`
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A D	X86ISelLowering.cpp	1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation ------- 4012 SDValue Lo = extractSubVector(Op, 0, DAG, dl, SizeInBits / 2); splitVector() local 4411 createUnpackShuffleMask(EVT VT,SmallVectorImpl<int> & Mask,bool Lo,bool Unary) createUnpackShuffleMask() argument 4431 createSplat2ShuffleMask(MVT VT,SmallVectorImpl<int> & Mask,bool Lo) createSplat2ShuffleMask() argument 6135 int lo = UsedInputs.size() * MaskWidth; resolveTargetShuffleInputsAndMask() local 7744 SDValue LO = DAG.getUNDEF(NewVT); ExpandHorizontalBinOp() local 8444 SDValue Lo = extract128BitVector(SrcVec, 0, DAG, DL); createVariablePermute() local 9109 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, LowerAVXCONCAT_VECTORS() local 9195 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, LowerCONCAT_VECTORSvXi1() local 10104 __anon973982072102(SDValue Lo, SDValue Hi) lowerShuffleAsVTRUNC() argument 10568 SDValue Lo = DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2, lowerShuffleAsBlend() local 10743 int Lo = Lane, Mid = Lane + NumHalfLaneElts, Hi = Lane + NumLaneElts; lowerShuffleAsUNPCKAndPermute() local 10961 __anon973982072602(SDValue Lo, SDValue Hi, int RotAmt, int Ofs) lowerShuffleAsByteRotateAndPermute() argument 11217 SDValue Lo, Hi; matchShuffleAsElementRotate() local 11318 SDValue Lo = V1, Hi = V2; lowerShuffleAsByteRotate() local 11381 SDValue Lo = V1, Hi = V2; lowerShuffleAsVALIGN() local 11840 SDValue Lo = DAG.getBitcast( lowerShuffleAsSpecificZeroOrAnyExtend() local 14524 SDValue Lo = HalfBlend(LoMask); splitAndLowerShuffle() local 18820 SDValue Lo, Hi; LowerShiftParts() local 20027 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v8i1, In, SplitAndExtendv16i1() local 20166 SDValue Lo, Hi; truncateVectorWithPACK() local 20359 if (SDValue Lo = isUpperSubvectorUndef(In, DL, DAG)) { LowerTruncateVecPackWithSignBits() local 20402 if (SDValue Lo = isUpperSubvectorUndef(In, DL, DAG)) { LowerTruncateVecPack() local 20471 SDValue Lo, Hi; LowerTruncateVecI1() local 20528 SDValue Lo, Hi; LowerTRUNCATE() local 22154 SDValue Lo = LowerVectorAllEqual() local 24276 SDValue Lo = DAG.getNode(Opc, dl, HalfVT, In); LowerEXTEND_VECTOR_INREG() local 25134 SDValue Lo, Hi; getMaskNode() local 26440 SDValue LO, HI; expandIntrinsicWChainHelper() local 27757 SDValue Lo = Op0; LowerVectorCTLZInRegLUT() local 28603 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, LoVTs, LHSLo, RHSLo); LowerMULO() local 29149 SDValue Lo = DAG.getBitcast(MVT::v4i32, getUnpackl(DAG, dl, VT, Amt, Z)); convertShiftLeftToScale() local 29567 SDValue Lo = DAG.getNode(Opc, dl, ExtVT, RLo, ALo); LowerShift() local 29731 SDValue Lo = DAG.getBitcast(ExtVT, getUnpackl(DAG, DL, VT, Op1, Op0)); LowerFunnelShift() local 29775 SDValue Lo = DAG.getNode(ShiftOpc, DL, ExtVT, RLo, ALo); LowerFunnelShift() local 29946 SDValue Lo = DAG.getBitcast(ExtVT, getUnpackl(DAG, DL, VT, R, R)); LowerRotate() local 29970 SDValue Lo = DAG.getNode(ShiftOpc, DL, ExtVT, RLo, ALo); LowerRotate() local 30100 SDValue Lo = DAG.getNode(ISD::MUL, DL, VT, R, Scale); LowerRotate() local 30775 SDValue Lo, Hi; getPMOVMSKB() local 30786 SDValue Lo, Hi; getPMOVMSKB() local 30810 SDValue Lo, Hi; LowerBITCAST() local 31111 SDValue Lo = DAG.getNode(ISD::AND, DL, VT, In, NibbleMask); LowerBITREVERSE() local 31165 SDValue Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, X); LowerPARITY() local 31184 SDValue Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, X); LowerPARITY() local 31775 SDValue Lo, Hi; LowerCVTPS2PH() local 32023 SDValue Lo, Hi; ReplaceNodeResults() local 32035 SDValue Lo, Hi; ReplaceNodeResults() local 32268 SDValue Lo, Hi; ReplaceNodeResults() local 32323 SDValue Lo = DAG.getVectorShuffle(MVT::v4i32, dl, In, SignBits, ReplaceNodeResults() local 32356 SDValue Lo = getEXTEND_VECTOR_INREG(N->getOpcode(), dl, LoVT, In, DAG); ReplaceNodeResults() local 33002 SDValue Lo, Hi; ReplaceNodeResults() local 37707 SDValue Lo = MatchHalf(0, ShufMask[0], ShufMask[1]); matchBinaryPermuteShuffle() local 37931 SDValue Lo = CanonicalizeShuffleInput(RootVT, V1); combineX86ShuffleChain() local 38551 int lo = I * WideMask.size(); combineX86ShuffleChainWithExtract() local 38784 SDValue Lo = isInRange(WideMask128[0], 0, 2) ? BC0 : BC1; canonicalizeShuffleMaskWithHorizOp() local 39191 int Lo = I * Mask.size(); combineX86ShufflesRecursively() local 39286 int Lo = OpIdx * Mask.size(); combineX86ShufflesRecursively() local 41669 int Lo = Src * NumElts; SimplifyDemandedVectorEltsForTargetNode() local 43312 SDValue Lo, Hi; combineMinMaxReduction() local 43419 SDValue Lo, Hi; combinePredicateReduction() local 43449 SDValue Lo, Hi; combinePredicateReduction() local 43794 int Lo = Scale * ExtractIdx; combineExtractWithShuffle() local 43997 SDValue Lo = getUnpackl(DAG, DL, VecVT, Rdx, DAG.getUNDEF(VecVT)); combineArithReduction() local 44041 SDValue Lo, Hi; combineArithReduction() local 44088 SDValue Lo, Hi; combineArithReduction() local 44119 SDValue Lo = extract128BitVector(Rdx, 0, DAG, DL); combineArithReduction() local 47178 SDValue Lo, Hi; combineHorizOpWithShuffle() local 50434 SDValue Lo = DAG.getBuildVector(MVT::v32i1, dl, combineStore() local [all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A D	ARMISelLowering.cpp	1 //===- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------- 2223 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, LowerCallResult() local 3445 SDValue Lo, Hi; LowerWRITE_REGISTER() local 4139 SDValue Lo, Hi; LowerINTRINSIC_WO_CHAIN() local 6096 SDValue Lo = Tmp0.getValue(0); LowerFCOPYSIGN() local 6263 SDValue Lo, Hi; ExpandBITCAST() local 6329 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift, LowerShiftRightParts() local 6378 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LowerShiftLeftParts() local 6728 SDValue Lo, Hi; Expand64BitShift() local 6748 SDValue Lo, Hi; Expand64BitShift() local 7149 SDValue Lo = DAG.getConstant(INTVal.trunc(32), DL, MVT::i32); LowerConstantFP() local 8941 SDValue Lo = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, FromVT, V1); LowerVECTOR_SHUFFLE() local 9357 SDValue Lo, Hi; LowerTruncate() local 10083 SDValue Lo, Hi; WinDBZCheckDenominator() local 10162 SDValue Lo = Result.getValue(DAG.getDataLayout().isLittleEndian() ? 0 : 1); LowerLOAD() local 10219 SDValue Lo = DAG.getNode( LowerSTORE() local 10384 SDValue Lo, Hi; LowerVecReduceMinMax() local 10486 SDValue Lo = ReplaceCMP_SWAP_64Results() local 10695 SDValue Lo, Hi; ReplaceLongIntrinsic() local 12821 SDValue Lo = AddcNode->getOperand(1); AddCombineTo64BitSMLAL16() local 15664 SDValue Lo, Hi; PerformInsertSubvectorCombine() local 21522 Value Lo = Builder.CreateExtractValue(LoHi, 0, "lo"); emitLoadLinked() local 21565 Value Lo = Builder.CreateTrunc(Val, Int32Ty, "lo"); emitStoreConditional() local [all...]
/freebsd-src/sys/dev/qlnx/qlnxe/
H A D	ecore_dbg_fw_funcs.c	2 * Copyright (c) 2017-2018 Cavium, Inc. 168 return (r[0] < (r[1] - imm[0])); in cond8() 226 * Addresses are in bytes, sizes are in quad-regs. 363 …, val_width, amount) (((val) \| ((val) << (val_width))) >> (amount)) & ((1 << (val_width)) - 1) 371 #define FIELD_BIT_MASK(type, field) (((1 << FIELD_BIT_SIZE(type, field)) - 1) << FIELD_DWORD_SHIF… 390 #define NUM_EXTRA_DBG_LINES(block_desc) (1 + (block_desc->has_latency_events ? 1 : 0)) 391 #define NUM_DBG_LINES(block_desc) (block_desc->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc)) 457 #define MAX_CYCLE_VALUES_MASK ((1 << VALUES_PER_CYCLE) - 1) 1529 "int-buf", 1535 "pci-buf" [all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A D	SIISelLowering.cpp	`1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ------- 5451 SDValue Lo, Hi; splitUnaryVectorOp() local 6869 SDValue Lo, Hi; lowerEXTRACT_VECTOR_ELT() local 7042 SDValue Lo = DAG.getBuildVector(HalfVT, SL, LoOps); lowerBUILD_VECTOR() local 7098 SDValue Lo = Op.getOperand(0); lowerBUILD_VECTOR() local 10242 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1); LowerSELECT() local 12686 SDValue Lo = N0.getOperand(0); performFCanonicalizeCombine() local [all...]`
/freebsd-src/sys/dev/bxe/
H A D	ecore_hsi.h	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved. 145 /* Up to 16 bytes of NULL-terminated string / 164 (if multiple found, priority order is: NC-SI, UMP, IPMI) / 169 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 170 (can only be used when an add-in board, not BMC, pulls-down SPIO4) / 172 / Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 173 (can only be used when an add-in board, not BMC, pulls-down SPIO4) / 175 / Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP [all …]
/freebsd-src/contrib/ncurses/misc/
H A D	terminfo.src	7 # bug-ncurses@gnu.org 19 # under the ncurses MIT-style license. That was the effect of the agreement 33 # some portions of the data are derivative work under a compatible MIT-style 36 #------------------------------------------------------------------------------ 37 # https://invisible-island.net/ncurses/ncurses.faq.html#terminfo_copying 38 # https://invisible-island.net/personal/copyrights.html#removing_notes 39 #------------------------------------------------------------------------------ 48 # Please e-mail changes to terminfo@thyrsus.com; the old termcap@berkeley.edu 54 # This file describes the capabilities of various character-cell terminals, 55 # as needed by software such as screen-oriented editors. [all …]
/freebsd-src/tests/sys/geom/class/eli/
H A D	testvect.h	1 /* Test Vectors for PBKDF2-SHA512 / 3 …\300!tp\367\257\347c'\000\243F\246\376\274H\263\312m\336\304\3515P\222Cb\037-\313W\0067\232\024%\2… 4 …356?alD\231I[%A\372\367\027\267,\303\022\324\004\302a\302t\257\306S\251\250;-pa\246Z\200\003+\026… 10 …4\334\005O,\374\225\234\014\266\365\030i6\210a\205", 100, "\220\006\216\2420-8m\2766\353(6\212\306… 16 …00, "\334\222G\300~'\042LS\0218\006,\261\207]\277\245GH\007\246\357f\205\325-\3044\337\347\007\373… 17 …212\377\257\177\350f\276\330\3035\204\215\327f\256\300\364\212\271\306q\242?-\307\324\317y^\201t\2… 18 …{ "\234^\035\320rt-B", 8, "\357\274\204\366N9\273:\216\331,D\300t\320\361\324F\313\220E\250u\203\3… 25 …5\317 w\034u?", 300, "\276\317.\310Gj \217\3502.za\021\230\322C6\255\301\354-\263\247\002\352\377\… 26 …{ "\265G\357\330S\302?8", 8, "7S-\203\036\340\015\356\027\253\302\376\222\037\2276\0141\|p\255\313\… 32 …{ "p(\256-\313\020{\300", 8, "\334\310\227\225J\356\360\307!\353\023\332\|\214\306\036\026\253\|-\26… [all …]
/freebsd-src/contrib/llvm-project/openmp/runtime/src/
H A D	kmp.h	`3 * kmp.h -- KPTS runtime header file. 6 //===-------- 4423 kmp_int64 lo; // lower global() member [all...]`
/freebsd-src/contrib/ntp/ntpq/
H A D	ntpq-subs.c	`2 * ntpq-subs.c - subroutines which are called to perform ntpq commands. 11 #include "ntpq-opts.h" 159 { "-4\|-6", "", "", "" }, 162 { "-4\|-6", "", "", "" }, 165 { "-4\|-6", "", "", "" }, 168 { "-4\|-6", "", "", "" }, 171 { "-4\|-6", "", "", "" }, 176 { "config-from-file", config_from_file, { NTP_STR, NO, NO, NO }, 210 { "-4\|-6", "", "", "" }, "" } 222 #define MRU_GOT_LAST 0x2 [all …]`
/freebsd-src/contrib/llvm-project/clang/lib/CodeGen/
H A D	CGBuiltin.cpp	`1 //===---- CGBuiltin.cpp - Emit LLVM Code for builtins ----- [all...]`
/freebsd-src/contrib/llvm-project/clang/lib/Sema/
H A D	SemaExpr.cpp	`1 //===--- SemaExpr.cpp - Semantic Analysis for Expressions ------ 15296 LangOptions LO = S.getLangOpts(); CheckIndirectionOperand() local [all...]`
/freebsd-src/contrib/sqlite3/
H A D	sqlite3.c	`17 language. The code for the "sqlite3" command-line shell is also in a 20 The content in this amalgamation comes from Fossil check-in 51 NO_TEST - The branches on this line are not 56 OPTIMIZATION-IF-TRUE - This branch is allowed to always be false 60 OPTIMIZATION-IF-FALSE - This branch is allowed to always be true 64 PREVENTS-HARMLES 24473 int Y, M, D, A, B, X1, X2; computeJD() local 36834 unsigned int lo, hi; sqlite3Hwtime() local [all...]`