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/freebsd-src/sys/contrib/device-tree/Bindings/display/
H A Dallwinner,sun4i-a10-tcon.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tcon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Timings Controller (TCON)
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The TCON acts as a timing controller for RGB, LVDS and TV
18 "#clock-cells":
23 - const: allwinner,sun4i-a10-tcon
[all …]
H A Dingenic,lcd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/ingenic,lcd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs LCD controller
10 - Paul Cercueil <paul@crapouillou.net>
14 pattern: "^lcd-controller@[0-9a-f]+$"
18 - ingenic,jz4740-lcd
19 - ingenic,jz4725b-lcd
20 - ingenic,jz4760-lcd
[all …]
H A Dingenic,lcd.txt1 Ingenic JZ47xx LCD driver
4 - compatible: one of:
5 * ingenic,jz4740-lcd
6 * ingenic,jz4725b-lcd
7 * ingenic,jz4770-lcd
8 - reg: LCD registers location and length
9 - clocks: LCD pixclock and device clock specifiers.
11 - clock-names: "lcd_pclk" and "lcd"
12 - interrupts: Specifies the interrupt line the LCD controller is connected to.
20 power-supply = <&vcc>;
[all …]
H A Dmarvell,pxa2xx-lcdc.txt1 PXA LCD Controller
2 ------------------
5 - compatible : one of these
6 "marvell,pxa2xx-lcdc",
7 "marvell,pxa270-lcdc",
8 "marvell,pxa300-lcdc"
9 - reg : should contain 1 register range (address and length).
10 - interrupts : framebuffer controller interrupt.
11 - clocks: phandle to input clocks
14 - lcd-supply: A phandle to a power regulator that controls the LCD voltage.
[all …]
H A Datmel,lcdc.txt2 -----------------------------------------------------
5 - compatible :
6 "atmel,at91sam9261-lcdc" ,
7 "atmel,at91sam9263-lcdc" ,
8 "atmel,at91sam9g10-lcdc" ,
9 "atmel,at91sam9g45-lcdc" ,
10 "atmel,at91sam9g45es-lcdc" ,
11 "atmel,at91sam9rl-lcdc" ,
12 - reg : Should contain 1 register ranges(address and length).
15 - interrupts : framebuffer controller interrupt
[all …]
H A Dintel,keembay-display.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/intel,keembay-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Keem Bay display controller
10 - Anitha Chrisanthus <anitha.chrisanthus@intel.com>
11 - Edmond J Dea <edmund.j.dea@intel.com>
15 const: intel,keembay-display
19 - description: LCD registers range
21 reg-names:
[all …]
H A Darm,pl11x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm PrimeCell Color LCD Controller PL110/PL111
10 - Liviu Dudau <Liviu.Dudau@arm.com>
11 - Andre Przywara <andre.przywara@arm.com>
14 The Arm Primcell PL010/PL111 is an LCD controller IP, than scans out
16 a variety of LCD panels.
24 - arm,pl110
25 - arm,pl111
[all …]
H A Dst,stm32-ltdc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-ltdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 lcd-tft display controller
10 - Philippe Cornu <philippe.cornu@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
15 const: st,stm32-ltdc
22 - description: events interrupt line.
23 - description: errors interrupt line.
[all …]
H A Drenesas,shmobile-lcdc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/renesas,shmobile-lcdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas SH-Mobile LCD Controller (LCDC)
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - renesas,r8a7740-lcdc # R-Mobile A1
17 - renesas,sh73a0-lcdc # SH-Mobile AG5
30 Some of the optional clocks are model-dependent (e.g. "video" (a.k.a.
[all …]
H A Dcirrus,clps711x-fb.txt4 - compatible: Shall contain "cirrus,ep7209-fb".
5 - reg : Physical base address and length of the controller's registers +
7 - clocks : phandle + clock specifier pair of the FB reference clock.
8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
11 - bits-per-pixel: Bits per pixel.
12 - ac-prescale : LCD AC bias frequency. This frequency is the required
13 AC bias frequency for a given manufacturer's LCD plate.
14 - cmap-invert : Invert the color levels (Optional).
17 - lcd-supply: Regulator for LCD supply voltage.
[all …]
H A Dsitronix,st7586.txt4 - compatible: "lego,ev3-lcd".
5 - a0-gpios: The A0 signal (since this binding is for serial mode, this is
6 the pin labeled D1 on the controller, not the pin labeled A0)
7 - reset-gpios: Reset pin
9 The node for this driver must be a child node of a SPI controller, hence
10 all mandatory properties described in ../spi/spi-bus.txt must be specified.
13 - rotation: panel rotation in degrees counter clockwise (0,90,180,270)
17 compatible = "lego,ev3-lcd";
19 spi-max-frequency = <10000000>;
20 a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/panel/
H A Dolimex,lcd-olinuxino.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/olimex,lcd-olinuxino.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Olimex Ltd. LCD
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/auxdisplay/
H A Dhit,hd44780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dimg-ascii-lcd.txt1 Binding for ASCII LCD displays on Imagination Technologies boards
4 - compatible : should be one of:
5 "img,boston-lcd"
6 "mti,malta-lcd"
7 "mti,sead3-lcd"
9 Required properties for "img,boston-lcd":
10 - reg : memory region locating the device registers
12 Required properties for "mti,malta-lcd" or "mti,sead3-lcd":
13 - regmap: phandle of the system controller containing the LCD registers
14 - offset: offset in bytes to the LCD registers within the system controller
H A Dimg,ascii-lcd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/auxdisplay/img,ascii-lc
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/display/armada/
H A Dmarvell,dove-lcd.txt4 - compatible: value should be "marvell,dove-lcd".
5 - reg: base address and size of the LCD controller
6 - interrupts: single interrupt number for the LCD controller
7 - port: video output port with endpoints, as described by graph.txt
11 - clocks: as described by clock-bindings.txt
12 - clock-names: as described by clock-bindings.txt
13 "axiclk" - axi bus clock for pixel clock
14 "plldivider" - pll divider clock for pixel clock
15 "ext_ref_clk0" - external clock 0 for pixel clock
16 "ext_ref_clk1" - external clock 1 for pixel clock
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/microchip/
H A Dat91sam9x5_lcd.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
4 * LCD controller.
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,at91sam9x5-hlcdc";
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
[all …]
H A Dsama5d3_lcd.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with
4 * LCD support
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,sama5d3-hlcdc";
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/tilcdc/
H A Dtilcdc.txt1 Device-Tree bindings for tilcdc DRM driver
4 - compatible: value should be one of the following:
5 - "ti,am33xx-tilcdc" for AM335x based boards
6 - "ti,da850-tilcdc" for DA850/AM18x/OMAP-L138 based boards
7 - interrupts: the interrupt number
8 - reg: base address and size of the LCDC device
11 - ti,hwmods: Name of the hwmod associated to the LCDC
14 - max-bandwidth: The maximum pixels per second that the memory
15 interface / lcd controller combination can sustain
16 - max-width: The maximum horizontal pixel width supported by
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/samsung/
H A Dsamsung,exynos7-decon.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
16 DECON (Display and Enhancement Controller) is the Display Controller for the
[all …]
/freebsd-src/sys/contrib/device-tree/src/mips/ingenic/
H A Djz4740.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
16 compatible = "ingenic,xburst-mxu1.0";
20 clock-names = "cpu";
24 cpuintc: interrupt-controller {
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8183-kukui-kodama.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8183-kukui.dtsi"
8 #include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
11 ppvarn_lcd: ppvarn-lc
[all...]
/freebsd-src/sys/contrib/device-tree/src/mips/mti/
H A Dmalta.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/mips-gic.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 cpu_intc: interrupt-controller {
17 compatible = "mti,cpu-interrupt-controller";
19 interrupt-controller;
20 #interrupt-cells = <1>;
[all …]
/freebsd-src/sys/contrib/device-tree/src/mips/img/
H A Dboston.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 stdout-path = "uart0:115200";
23 #address-cells = <1>;
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/exynos/
H A Dexynos7-decon.txt1 Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON)
3 DECON (Display and Enhancement Controller) is the Display Controller for the
5 buffer to an external LCD interface.
8 - compatible: value should be "samsung,exynos7-decon";
10 - reg: physical base address and length of the DECON registers set.
12 - interrupts: should contain a list of all DECON IP block interrupts in the
14 format depends on the interrupt controller used.
16 - interrupt-names: should contain the interrupt names: "fifo", "vsync",
20 - pinctrl-0: pin control group to be used for this controller.
22 - pinctrl-names: must contain a "default" entry.
[all …]

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