| /freebsd-src/sys/contrib/device-tree/Bindings/ufs/ |
| H A D | ufshcd-pltfrm.txt | 3 UFSHC nodes are defined to describe on-chip UFS host controllers.
7 - compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0"
10 SoC-specific compatible along with "qcom,ufshc" and
12 "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
13 "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
14 "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
15 "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
16 "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
17 "qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
18 "qcom,sm8350-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
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| H A D | ufs-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/ufs-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alim Akhtar <alim.akhtar@samsung.com>
11 - Avri Altman <avri.altman@wdc.com>
16 clock-names: true
18 freq-table-hz:
21 - description: Minimum frequency for given clock in Hz
22 - description: Maximum frequency for given clock in Hz
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| H A D | qcom,ufs.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schema
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| /freebsd-src/sys/contrib/device-tree/Bindings/media/i2c/ |
| H A D | maxim,max9286.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jacopo Mondi <jacopo+renesas@jmondi.org>
12 - Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
13 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 - Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
18 Serial Links (GMSL) and outputs them on a CSI-2 D-PHY port using up to 4 data
19 lanes.
24 serializer will output it on a local I2C bus. In the other direction all I2C
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| /freebsd-src/sys/contrib/alpine-hal/ |
| H A D | al_hal_pcie.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
43 * - Port initialization
44 * - Link operation
45 * - Interrupts transactions generation (Endpoint mode).
46 * - Configuration Access management functions
47 * - Internal Translation Unit programming
50 * - PCIe transactions generation and reception (except interrupts as mentioned
53 * - Configuration Access: those transactions are generated automatically by
57 * - Interrupt Handling.
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| H A D | al_hal_pcie_w_reg.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
376 * - If MSI-X is enabled and auto_clear control bit =TRUE, automatically
377 * cleared after MSI-X message associated with this specific interrupt
378 * bit is sent (MSI-X acknowledge is received).
379 * - Software can set a bit in this register by writing 1 to the
381 * Write-0 clears a bit. Write-1 has no effect.
382 * - On CPU Read - If clear_on_read control bit =TRUE, automatically
400 * If Auto-mask control bit =TRUE, automatically set to 1 after MSI-X
408 * Used when auto-mask control bit=True. Enables CPU to clear a specific
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| /freebsd-src/sys/cam/ |
| H A D | cam_ccb.h | 1 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
75 CAM_DIR_BOTH = 0x00000000,/* Data direction (00:IN/OUT) */
76 CAM_DIR_IN = 0x00000040,/* Data direction (01:DATA IN) */
77 CAM_DIR_OUT = 0x00000080,/* Data direction (10:DATA OUT) */
78 CAM_DIR_NONE = 0x000000C0,/* Data direction (11:no data) */
79 CAM_DIR_MASK = 0x000000C0,/* Data direction Mask */
129 /* Non-immediate function code */
135 /* Common function commands: 0x00->0x0F */
168 /* SCSI Control Functions: 0x10->0x1F */
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterPressure.h | 1 //===- RegisterPressure.h - Dynamic Register Pressure -----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
59 /// TopIdx and BottomIdx. During pressure computation, the maximum pressure per
61 /// computed, the live-in and live-out sets are recorded.
98 /// Pressure increments are tiny, typically 1-2 units, and this is only for
116 return PSetID - 1; in getPSet()
121 return (PSetID - 1) & std::numeric_limits<uint16_t>::max(); in getPSetOrMax()
138 /// empty SmallVector than ever need to be tracked per register class. If more
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| /freebsd-src/lib/libpmc/pmu-events/arch/x86/cascadelakex/ |
| H A D | uncore-other.json | 10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
20 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
164 "ScaleUnit": "7.11E-06Bytes",
174 "ScaleUnit": "7.11E-06Bytes",
355 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
360 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory st…
365 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
370 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory s…
375 …"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory writ…
380 …"PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes iss…
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| /freebsd-src/lib/libpmc/pmu-events/arch/x86/skylakex/ |
| H A D | uncore-other.json | 10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
20 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
164 "ScaleUnit": "7.11E-06Bytes",
174 "ScaleUnit": "7.11E-06Bytes",
355 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
360 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory st…
365 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
370 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory s…
375 …"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory writ…
380 …"PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes iss…
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| /freebsd-src/contrib/ofed/opensm/man/ |
| H A D | opensm.8 | 4 opensm \- InfiniBand subnet manager and administration (SM/SA)
8 [\-\-version]]
9 [\-F | \-\-config <file_name>]
10 [\-c(reate-config) <file_name>]
11 [\-g(uid) <GUID in hex>]
12 [\-l(mc) <LMC>]
13 [\-p(riority) <PRIORITY>]
14 [\-\-smkey <SM_Key>]
15 [\-\-sm_sl <SL number>]
16 [\-r(eassign_lids)]
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| /freebsd-src/contrib/ofed/opensm/opensm/ |
| H A D | osm_ucast_dfsssp.c | 2 * Copyright (c) 2004-2008 Voltaire, Inc. All rights reserved.
3 * Copyright (c) 2002-2015 Mellanox Technologies LTD. All rights reserved.
4 * Copyright (c) 1996-2003 Intel Corporation. All rights reserved.
5 * Copyright (c) 2009-2015 ZIH, TU Dresden, Federal Republic of Germany. All rights reserved.
6 * Copyright (C) 2012-2017 Tokyo Institute of Technology. All rights reserved.
18 * - Redistributions of source code must retain the above
22 * - Redistributions in binary form must reproduce the above
40 * Implementation of OpenSM (deadlock-free) single-source-shortest-path routing
109 uint8_t *vls; /* matrix form assignment lid X lid -> virtual lane */
114 uint32_t num_pairs; /* number of src->dest pairs incremented in path adding step */
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| /freebsd-src/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGOpenMPRuntimeGPU.cpp | 1 //===---- CGOpenMPRuntimeGPU.cpp - Interface to OpenMP GPU Runtimes ----===//
5 // SPDX-Licens
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| /freebsd-src/sys/dev/bnxt/bnxt_en/ |
| H A D | hsi_struct_def.h | 1 /*-
34 * Copyright(c) 2001-2024, Broadcom. All rights reserved. The
71 * * 0x0-0xFFF8 - The function ID
72 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
73 * * 0xFFFD - Reserved for user-space HWRM interface
74 * * 0xFFFF - HWRM
122 /* Engine CKV - The Alias key EC curve and ECC public key information. */
124 /* Engine CKV - Initialization vector. */
126 /* Engine CKV - Authentication tag. */
128 /* Engine CKV - The encrypted data. */
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedA55.td | 1 //==- AArch64SchedCortexA55.td - ARM Cortex-A55 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for the ARM Cortex-A55 processors. Note
10 // that this schedule is currently used as the default for -mcpu=generic. As a
12 // Cortex-A55, instead aiming to be a good compromise between different cpus.
14 //===----------------------------------------------------------------------===//
16 // ===---------------------------------------------------------------------===//
17 // The following definitions describe the per-operand machine model.
20 // Cortex-A55 machine model for scheduling and other instruction cost heuristics.
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| /freebsd-src/sys/dev/qlnx/qlnxe/ |
| H A D | reg_addr.h | 2 * Copyright (c) 2017-2018 Cavium, Inc.
56 …DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line)…
57 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line)…
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 … // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo push overflow 5…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
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| /freebsd-src/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | sm6125.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-binding
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| H A D | sc8280xp.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280x
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| H A D | msm8996.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm899
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| H A D | msm8998.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm899
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| H A D | sc8180x.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8180
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| H A D | sa8775p.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interconnect/qcom,icc.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-binding
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| /freebsd-src/sys/dev/ice/ |
| H A D | ice_lib.c | 1 /* SPDX-License-Identifier: BSD-3-Clause */
128 u16 ethertype, u16 direction,
267 * ice_map_bar - Map PCIe BAR memory in ice_map_bar()
278 if (bar->res != NULL) { in ice_map_bar()
283 bar->rid = PCIR_BAR(bar_num);
284 bar->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &bar->ri
9090 ice_add_ethertype_to_list(struct ice_vsi * vsi,struct ice_list_head * list,u16 ethertype,u16 direction,enum ice_sw_fwd_act_type action) ice_add_ethertype_to_list() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 1 //===- SLPVectorizer.cpp - A bottom up SLP Vectorizer --------
2000 for (unsigned Lane = 0, Lanes = getNumLanes(); Lane != Lanes; ++Lane) getVL() local
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| /freebsd-src/sys/dev/sfxge/common/ |
| H A D | efx_regs_mcdi.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved.
32 /* Power-on reset state */
54 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
57 /* The rest of these are firmware-defined */
65 /* Values to be written to the per-port status dword in shared
94 * | | \--- Response
95 * | \------- Error
96 * \------------------------------ Resync (always set)
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