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/freebsd-src/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dbaikal,bt1-l2-ctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 L2-cache Control Block
11 - Serge Semin <fancer.lancer@gmail.com>
14 By means of the System Controller Baikal-T1 SoC exposes a few settings to
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
17 L2-cache controller block is responsible for the tuning. Its DT node is
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/cache/
H A Dbaikal,bt1-l2-ctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 L2-cache Control Block
11 - Serge Semin <fancer.lancer@gmail.com>
14 By means of the System Controller Baikal-T1 SoC exposes a few settings to
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
17 L2-cache controller block is responsible for the tuning. Its DT node is
[all …]
H A Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
21 Note 1: The description in this document doesn't apply to integrated L2
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
23 integrated L2 controllers are assumed to be all preconfigured by
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/icelakex/
H A Dmemory.json27 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
37 …s when the latency from first dispatch to completion is greater than 128 cycles. Reported latency…
43 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
53 …ds when the latency from first dispatch to completion is greater than 16 cycles. Reported latency…
59 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
69 …s when the latency from first dispatch to completion is greater than 256 cycles. Reported latency…
75 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
85 …ds when the latency from first dispatch to completion is greater than 32 cycles. Reported latency…
91 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
101 …ds when the latency from first dispatch to completion is greater than 4 cycles. Reported latency …
[all …]
H A Dicx-metrics.json3 …Total pipeline cost of branch related instructions (used for program control-flow including functi…
4 … 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR…
9 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
10 …- INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) …
39 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
45 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
51 … "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
57 "BriefDescription": "The ratio of Executed- by Issued-Uops",
61 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
64 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/
H A Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
21 Note 1: The description in this document doesn't apply to integrated L2
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
23 integrated L2 controllers are assumed to be all preconfigured by
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/sapphirerapids/
H A Dmemory.json69 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
79 …s when the latency from first dispatch to completion is greater than 128 cycles. Reported latency…
85 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
95 …ds when the latency from first dispatch to completion is greater than 16 cycles. Reported latency…
101 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
111 …s when the latency from first dispatch to completion is greater than 256 cycles. Reported latency…
117 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
127 …ds when the latency from first dispatch to completion is greater than 32 cycles. Reported latency…
133 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
143 …ds when the latency from first dispatch to completion is greater than 4 cycles. Reported latency …
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/jaketown/
H A Dmemory.json8 …lears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores…
13 "BriefDescription": "Loads with latency value being above 128.",
26 "BriefDescription": "Loads with latency value being above 16.",
39 "BriefDescription": "Loads with latency value being above 256.",
52 "BriefDescription": "Loads with latency value being above 32.",
65 "BriefDescription": "Loads with latency value being above 4 .",
78 "BriefDescription": "Loads with latency value being above 512.",
91 "BriefDescription": "Loads with latency value being above 64.",
104 "BriefDescription": "Loads with latency value being above 8.",
117 …le stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/amdzen4/
H A Dcache.json5 …iption": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store all…
11 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for har…
17 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all…
23 "BriefDescription": "Demand data cache fills from local L2 cache.",
29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
35 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the…
41 "BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.",
47 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a d…
53 …"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (sa…
59 "BriefDescription": "Demand data cache fills from extension memory.",
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/ivytown/
H A Dmemory.json12 "BriefDescription": "Loads with latency value being above 128",
20 "PublicDescription": "Loads with latency value being above 128.",
26 "BriefDescription": "Loads with latency value being above 16",
34 "PublicDescription": "Loads with latency value being above 16.",
40 "BriefDescription": "Loads with latency value being above 256",
48 "PublicDescription": "Loads with latency value being above 256.",
54 "BriefDescription": "Loads with latency value being above 32",
62 "PublicDescription": "Loads with latency value being above 32.",
68 "BriefDescription": "Loads with latency value being above 4",
76 "PublicDescription": "Loads with latency value being above 4.",
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf610.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 next-level-cache = <&L2>;
12 L2: cache-controller@40006000 { label
13 compatible = "arm,pl310-cache";
15 cache-unified;
16 cache-level = <2>;
17 arm,data-latency = <3 3 3>;
18 arm,tag-latency = <2 2 2>;
/freebsd-src/lib/libpmc/pmu-events/arch/x86/skylakex/
H A Dmemory.json71 …"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions a…
106 …f the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores…
111 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
120 …s when the latency from first dispatch to completion is greater than 128 cycles. Reported latency…
126 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
135 …ds when the latency from first dispatch to completion is greater than 16 cycles. Reported latency…
141 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
150 …s when the latency from first dispatch to completion is greater than 256 cycles. Reported latency…
156 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
165 …ds when the latency from first dispatch to completion is greater than 32 cycles. Reported latency…
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/alderlake/
H A Dcache.json3 …talled due to an instruction cache or tlb miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
14 …the core is stalled due to an instruction cache or tlb miss which hit in DRAM or MMIO (Non-DRAM).",
25 … of cycles the core is stalled due to an instruction cache or tlb miss which hit in the L2 cache.",
47 … the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
58 …ber of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
69 … "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
104 "BriefDescription": "Counts the number of load ops retired that hit in the L2 cache.",
199 …"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or…
215 …"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or…
231 …"BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or…
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A Dcache.json5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 …ting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cro…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
[all …]
H A Drecommended.json4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/amdzen2/
H A Dcache.json5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
H A Drecommended.json4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A Dcache.json5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
H A Drecommended.json4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 Cache HWPF",
[all …]
/freebsd-src/sys/arm/arm/
H A Dpl310.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
72 mtx_lock_spin(&(sc)->sc_mtx); \
76 mtx_unlock_spin(&(sc)->sc_mtx); \
85 static const uint32_t g_l2cache_align_mask = (32 - 1);
94 {"arm,pl310", true}, /* Non-standard, FreeBSD. */
95 {"arm,pl310-cache", true},
132 device_printf(sc->sc_dev, "Early BRESP response: %s\n", in pl310_print_config()
134 device_printf(sc->sc_dev, "Instruction prefetch: %s\n", in pl310_print_config()
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A Dmemory.json8 …lears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores…
13 "BriefDescription": "Loads with latency value being above 128.",
26 "BriefDescription": "Loads with latency value being above 16.",
39 "BriefDescription": "Loads with latency value being above 256.",
52 "BriefDescription": "Loads with latency value being above 32.",
65 "BriefDescription": "Loads with latency value being above 4 .",
78 "BriefDescription": "Loads with latency value being above 512.",
91 "BriefDescription": "Loads with latency value being above 64.",
104 "BriefDescription": "Loads with latency value being above 8.",
117 …le stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/broadwell/
H A Dmemory.json34 … "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
59 …cription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
89 …following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores…
94 "BriefDescription": "Randomly selected loads with latency value being above 128",
104 "PublicDescription": "Counts randomly selected loads with latency value being above 128.",
110 "BriefDescription": "Randomly selected loads with latency value being above 16",
120 "PublicDescription": "Counts randomly selected loads with latency value being above 16.",
126 "BriefDescription": "Randomly selected loads with latency value being above 256",
136 "PublicDescription": "Counts randomly selected loads with latency value being above 256.",
142 "BriefDescription": "Randomly selected loads with latency value being above 32",
[all …]
/freebsd-src/contrib/wpa/src/l2_packet/
H A Dl2_packet_pcap.c2 * WPA Supplicant - Layer2 packet handling with libpcap/libdnet and WinPcap
3 * Copyright (c) 2003-2006, Jouni Malinen <j@w1.fi>
43 int l2_packet_get_own_addr(struct l2_packet_data *l2, u8 *addr) in l2_packet_get_own_addr() argument
45 os_memcpy(addr, l2->own_addr, ETH_ALEN); in l2_packet_get_own_addr()
51 static int l2_packet_init_libdnet(struct l2_packet_data *l2) in l2_packet_init_libdnet() argument
55 l2->eth = eth_open(l2->ifname); in l2_packet_init_libdnet()
56 if (!l2->eth) { in l2_packet_init_libdnet()
58 "Failed to open interface '%s' - eth_open: %s", in l2_packet_init_libdnet()
59 l2->ifname, strerror(errno)); in l2_packet_init_libdnet()
60 return -1; in l2_packet_init_libdnet()
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/powerpc/power9/
H A Dcache.json5 …ion": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set"
15 …"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (divisi…
30 "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3"
40 …sor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on t…
55 …The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 o…
70 …was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to …
80 …another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When …
85 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl…
90 …ecause the NTF instruction was a load that hit on an older store and it was waiting for store data"
100 …e processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 o…
/freebsd-src/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca9.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A9 MPCore (V2P-CA9)
8 * HBI-0191B
11 /dts-v1/;
12 #include "vexpress-v2m.dtsi"
15 model = "V2P-CA9";
18 compatible = "arm,vexpress,v2p-ca
164 L2: cache-controller@1e00a000 { global() label
[all...]

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