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Searched +full:jh7110 +full:- +full:pll (Results 1 – 9 of 9) sorted by relevance

/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dstarfive,jh7110-pll.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PLL Clock Generator
10 These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
11 Each PLL works in integer mode or fraction mode, with configuration
13 SYS-SYSCON node.
18 - Xingyu Wu <xingyu.wu@starfivetech.com>
22 const: starfive,jh7110-pll
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/freebsd-src/sys/contrib/device-tree/Bindings/soc/starfive/
H A Dstarfive,jh7110-syscon.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 SoC system controller
10 - William Qiu <william.qiu@starfivetech.com>
13 The StarFive JH7110 SoC system controller provides register information such
19 - items:
20 - const: starfive,jh7110-sys-syscon
21 - const: syscon
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/freebsd-src/sys/riscv/starfive/
H A Dstarfive_syscon.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
13 * On the JH7110, the PLL clock driver is a child of the sys-syscon device.
41 { "starfive,jh7110-sys-syscon", JH7110_SYSCON_SYS },
42 { "starfive,jh7110-aon-syscon", JH7110_SYSCON_AON },
43 { "starfive,jh7110-stg-syscon", JH7110_SYSCON_STG },
56 type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; in starfive_syscon_probe()
62 device_set_desc(dev, "JH7110 SYS syscon"); in starfive_syscon_probe()
65 device_set_desc(dev, "JH7110 AON syscon"); in starfive_syscon_probe()
68 device_set_desc(dev, "JH7110 STG syscon"); in starfive_syscon_probe()
/freebsd-src/sys/dev/clk/starfive/
H A Djh7110_clk_pll.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 #include <dt-bindings/clock/starfive,jh7110-crg.h>
50 sc->dacpd_mask = PLL## id ##_DACPD_MASK; \
51 sc->dsmpd_mask = PLL## id ##_DSMPD_MASK; \
52 sc->fbdiv_mask = PLL## id ##_FBDIV_MASK; \
53 sc->frac_mask = PLL## id ##_FRAC_MASK; \
54 sc->prediv_mask = PLL## id ##_PREDIV_MASK; \
55 sc->postdiv1_mask = PLL## id ##_POSTDIV1_MASK; \
60 sc->dacpd_shift = PLL## id ##_DACPD_SHIFT; \
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H A Djh7110_clk_sys.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 /* Clocks for JH7110 SYS group. PLL driver must be attached before this. */
31 #include <dt-bindings/clock/starfive,jh7110-cr
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H A Djh7110_clk_aon.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
9 /* Clocks for JH7110 AON group. PLL driver must be attached before this. */
29 #include <dt-bindings/clock/starfive,jh7110-crg.h>
35 { "starfive,jh7110-aoncrg", 1 },
67 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in jh7110_clk_aon_probe()
70 device_set_desc(dev, "StarFive JH7110 AON clock generator"); in jh7110_clk_aon_probe()
83 sc->reset_status_offset = AONCRG_RESET_STATUS; in jh7110_clk_aon_attach()
84 sc->reset_selector_offset = AONCRG_RESET_SELECTOR; in jh7110_clk_aon_attach()
86 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); in jh7110_clk_aon_attach()
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H A Djh7110_clk_pll.h1 /* SPDX-License-Identifier: MIT */
3 * StarFive JH7110 PLL Clock Generator Driver
/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
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/freebsd-src/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pm
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