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/freebsd-src/sys/contrib/device-tree/Bindings/reserved-memory/
H A Dreserved-memory.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/reserved-memory.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: /reserved-memory Child Node Common
10 - devicetree-spec@vger.kernel.org
13 Reserved memory is specified as a node under the /reserved-memory node. The
19 Each child of the reserved-memory node specifies one or more regions
25 Following the generic-names recommended practice, node names should
26 reflect the purpose of the node (ie. "framebuffer" or "dma-pool").
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H A Dshared-dma-pool.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/shared-dma-pool.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: /reserved-memory DMA pool
10 - devicetree-spec@vger.kernel.org
13 - $ref: reserved-memory.yaml
18 - const: shared-dma-pool
25 - const: restricted-dma-pool
30 When using this, the no-map and reusable properties must not
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/freebsd-src/sys/contrib/device-tree/Bindings/iommu/
H A Drockchip,iommu.txt1 Rockchip IOMMU
4 A Rockchip DRM iommu translates io virtual addresses to physical addresses for
9 - compatible : Should be "rockchip,iommu"
10 - reg : Address space for the configuration registers
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - interrupt-names : Interrupt name for the IOMMU instance
13 - #iommu-cells : Should be <0>. This indicates the iommu is a
14 "single-master" device, and needs no additional information
16 Documentation/devicetree/bindings/iommu/iommu.txt
17 - clocks : A list of clocks required for the IOMMU to be accessible by
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H A Drockchip,iommu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip IOMMU
10 - Heiko Stuebner <heiko@sntech.de>
13 A Rockchip DRM iommu translates io virtual addresses to physical addresses for
17 For information on assigning IOMMU controller to its peripheral devices,
18 see generic IOMMU bindings.
23 - enum:
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H A Diommu.txt5 IOMMU device node:
8 An IOMMU can provide the following services:
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
34 "dma-ranges" property that describes how the physical address space of the
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/freebsd-src/sys/contrib/device-tree/Bindings/pci/
H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generi
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H A Dlayerscape-pci.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
22 "fsl,ls1043a-pcie"
23 "fsl,ls1012a-pcie"
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/freebsd-src/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-host1x.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierr
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/freebsd-src/sys/x86/iommu/
H A Dintel_utils.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
64 #include <dev/iommu/busdma_iommu.h>
65 #include <x86/iommu/intel_reg.h>
66 #include <x86/iommu/x86_iommu.h>
67 #include <x86/iommu/intel_dmar.h>
102 * 6-leve
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H A Dintel_idpgtbl.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
66 #include <dev/iommu/busdma_iommu.h>
67 #include <x86/iommu/intel_reg.h>
68 #include <x86/iommu/x86_iommu.h>
69 #include <x86/iommu/intel_dmar.h>
90 level, it is non-zer
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/freebsd-src/sys/contrib/device-tree/Bindings/crypto/
H A Dhisilicon,hip07-sec.txt4 - compatible: Must contain one of
5 - "hisilicon,hip06-sec"
6 - "hisilicon,hip07-sec"
7 - reg: Memory addresses and lengths of the memory regions through which
11 Regions 2-18 have registers for the 16 individual queues which are isolated
13 - interrupts: Interrupt specifiers.
14 Refer to interrupt-controller/interrupts.txt for generic interrupt client node
19 - dma-coherent: The driver assumes coherent dma is possible.
22 - iommus: The SEC units are behind smmu-v3 iommus.
23 Refer to iommu/arm,smmu-v3.txt for more information.
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/freebsd-src/sys/contrib/device-tree/Bindings/dma/
H A Dqcom_hidma_mgmt.txt18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
34 - max-read-transactions: This value is how many times a read burst is
36 - channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
41 Sub-nodes:
50 - compatible: must contain "qcom,hidma-1.0" for initial HW or
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/freebsd-src/sys/powerpc/ps3/
H A Dps3bus.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
50 #include "ps3-hvcall.h"
128 /* IOMMU interface */
160 if (device_find_child(parent, "ps3bus", -1) == NULL) in ps3bus_identify()
184 resource_list_init(&dinfo->resources); in ps3bus_resources_init()
187 thread = 32 - fl in ps3bus_resources_init()
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/freebsd-src/sys/amd64/vmm/amd/
H A Damdvi_hw.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
55 #include "io/iommu.h"
63 #define MOD_DEC(a, s, m) (((a) - (s)) % ((m) * (s)))
127 return (pci_cfgregread(softc->pci_seg, PCI_RID2BUS(softc->pci_rid), in amdvi_pci_read()
128 PCI_RID2SLOT(softc->pci_ri in amdvi_pci_read()
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/freebsd-src/sys/dev/iommu/
H A Diommu_gas.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
60 #include <dev/iommu/iommu.h>
61 #include <dev/iommu/iommu_gas.h>
62 #include <dev/iommu/iommu_msi.h>
66 #include <machine/iommu
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/freebsd-src/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8939.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-binding
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H A Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm891
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/freebsd-src/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gi
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H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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/freebsd-src/sys/amd64/vmm/intel/
H A Dvtd.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
42 #include "io/iommu.h"
132 nd = VTD_CAP_ND(vtdmap->cap); in vtd_max_domains()
160 /* Skip domain id 0 - it is reserved when Caching Mode field is set */ in domain_id()
163 if (dom->id == id) in domain_id()
189 if (VTD_DRHD_INCLUDE_PCI_ALL(drhd->Flags)) { in vtd_device_scope()
191 * From Intel VT-d arch spec, version 3.0: in vtd_device_scope()
200 end = (char *)drhd + drhd->Header.Length; in vtd_device_scope()
201 remaining = drhd->Header.Length - sizeof(ACPI_DMAR_HARDWARE_UNIT); in vtd_device_scope()
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/freebsd-src/sys/dev/virtio/block/
H A Dvirtio_blk.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
208 #define vtblk_modern(_sc) (((_sc)->vtblk_features & VIRTIO_F_VERSION_1) != 0)
219 static int vtblk_writecache_mode = -1;
237 #define VTBLK_MTX(_sc) &(_sc)->vtblk_mtx
253 * Each block request uses at least two segments - one for the header
321 sc->vtblk_dev = dev; in vtblk_attach()
325 bioq_init(&sc->vtblk_bioq); in vtblk_attach()
326 TAILQ_INIT(&sc->vtblk_dump_queue); in vtblk_attach()
327 TAILQ_INIT(&sc->vtblk_req_free); in vtblk_attach()
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/freebsd-src/sys/dev/ofw/
H A Dofw_bus_subr.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>.
59 if ((OF_getprop_alloc(node, "name", (void **)&obd->obd_name)) == -1) in ofw_bus_gen_setup_devinfo()
61 OF_getprop_alloc(node, "compatible", (void **)&obd->obd_compat); in ofw_bus_gen_setup_devinfo()
62 OF_getprop_alloc(node, "device_type", (void **)&obd->obd_typ in ofw_bus_gen_setup_devinfo()
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/freebsd-src/sys/kern/
H A Dsubr_bus_dma.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
109 for (; sglist_cnt > 0 && length != 0; sglist_cnt--, list++) { in _bus_dmamap_load_vlist()
113 KASSERT((offset < list->ds_len), in _bus_dmamap_load_vlist()
114 ("Invalid mid-segment offset")); in _bus_dmamap_load_vlist()
115 addr = (char *)(uintptr_t)list->ds_addr + offset; in _bus_dmamap_load_vlist()
116 ds_len = list->ds_len - offset; in _bus_dmamap_load_vlist()
120 length -= ds_len; in _bus_dmamap_load_vlist()
131 * Load a list of physical addresses.
140 for (; sglist_cnt > 0; sglist_cnt--, list++) { in _bus_dmamap_load_plist()
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/freebsd-src/sys/dev/netmap/
H A Dnetmap_mem2.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (C) 2012-2014 Matteo Landi
5 * Copyright (C) 2012-2016 Luigi Rizzo
6 * Copyright (C) 2012-2016 Giuseppe Lettieri
98 /* --
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