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/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
[all …]
H A Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
/freebsd-src/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110-starfive-visionfive-2-v1.3b.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
[all …]
/freebsd-src/sys/contrib/device-tree/include/dt-bindings/sound/
H A Dcs35l45.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
12 * cirrus,asp-sdout-hiz-ctrl
14 * TX_HIZ_UNUSED: TX pin high-impedance during unused slots.
15 * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
21 * Optional GPIOX Sub-nodes:
22 * The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
23 * sub-nodes for configuring the GPIO pins.
25 * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
30 * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/serial/
H A Dfsl-imx-uart.txt4 - compatible : Should be "fsl,<soc>-uart"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain uart interrupt
9 - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
11 - fsl,inverted-tx , fsl,inverted-rx : Indicate that the hardware attached
15 - rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
16 linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485
17 you must enable either the "uart-has-rtscts" or the "rts-gpios"
18 properties. In case you use "uart-has-rtscts" the signal that controls
20 and RTS_B is input, regardless of dte-mode.
[all …]
H A Dfsl-imx-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <festevam@gmail.com>
15 - const: fsl,imx1-uart
16 - const: fsl,imx21-uart
17 - items:
18 - enum:
19 - fsl,imx25-uart
[all …]
/freebsd-src/sys/contrib/device-tree/src/powerpc/
H A Deiger.dts11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
[all …]
H A Darches.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
24 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by U-Boot */
42 timebase-frequency = <0>; /* Filled in by U-Boot */
43 i-cache-line-size = <32>;
[all …]
H A Dklondike.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
16 dcr-parent = <&{/cpus/cpu@0}>;
24 #address-cells = <1>;
25 #size-cells = <0>;
31 clock-frequency = <300000000>; /* Filled in by U-Boot */
32 timebase-frequency = <300000000>; /* Filled in by U-Boot */
33 i-cache-line-size = <32>;
[all …]
H A Dglacier.dts4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
[all …]
H A Dobs600.dts8 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
15 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
32 #address-cells = <1>;
33 #size-cells = <0>;
39 clock-frequency = <0>; /* Filled in by U-Boot */
40 timebase-frequency = <0>; /* Filled in by U-Boot */
41 i-cache-line-size = <32>;
[all …]
H A Drainier.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
[all …]
H A Dmakalu.dts11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
[all …]
H A Dkilauea.dts4 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
[all …]
H A Dsequoia.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
[all …]
H A Dfsp2.dts12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by cuboot */
36 timebase-frequency = <0>; /* Filled in by cuboot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/microchip/
H A Dat91-kizbox2-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox2_common.dtsi - Device Tree Include file for
6 * Copyright (C) 2014-2018 Overkiz SAS
17 stdout-path = &dbgu;
26 clock-frequency = <32768>;
30 clock-frequency = <12000000>;
34 gpio-keys {
35 compatible = "gpio-keys";
37 button-prog {
41 wakeup-source;
[all …]
H A Dsama7g5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controlle
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-a64-oceanic-5205-5inmfd.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "sun50i-a64-sopine.dtsi"
12 compatible = "oceanic,5205-5inmfd", "allwinner,sun50i-a64";
20 stdout-path = "serial0:115200n8";
29 pinctrl-names = "default";
30 pinctrl-0 = <&rgmii_pins>;
31 phy-mode = "rgmii";
32 phy-handle = <&ext_rgmii_phy>;
33 phy-supply = <&reg_dc1sw>;
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/input/touchscreen/
H A Dazoteq,iqs7211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd-src/sys/dev/mii/
H A Dnsphyterreg.h3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
62 #define PHYSTS_MP_POLARITY 0x1000 /* polarity inverted */
65 #define PHYSTS_MP_DESCRLK 0x0200 /* de-scrambler lock */
85 #define MIPGSR_MSK_ANC 0x0800 /* mask auto-neg complete event */
96 #define PCSR_SINGLE_SD 0x8000 /* single-ended SD mode */
134 #define BTSCR_TX_SERIAL 0x0800 /* 10baseT TX serial mode */
150 #define PHYCTRL_LED_TXRX_MODE 0x0180 /* LED TX/RX mode */
167 #define TBTCTL_INV_POLARITY 0x0010 /* inverted polarity */
168 #define TBTCTL_AUTOPOL_DIS 0x0008 /* auto-polarity disable */
/freebsd-src/sys/contrib/device-tree/Bindings/input/rmi4/
H A Drmi_spi.txt10 - compatible: syna,rmi4-spi
11 - reg: Chip select address for the device
12 - #address-cells: Set to 1 to indicate that the function child nodes
14 - #size-cells: Set to 0 to indicate that the function child nodes do not
18 - interrupts: interrupt which the rmi device is connected to.
19 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
21 - spi-rx-delay-us: microsecond delay after a read transfer.
22 - spi-tx-delay-us: microsecond delay after a write transfer.
33 rmi4-spi-dev@0 {
34 compatible = "syna,rmi4-spi";
[all …]
/freebsd-src/sys/contrib/dev/athk/
H A Dkey.c25 #define REG_READ (common->ops->read)
26 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg)
28 if (common->ops->enable_write_buffer) \
29 common->ops->enable_write_buffer((_ah));
32 if (common->ops->write_flush) \
33 common->ops->write_flush((_ah));
45 void *ah = common->ah; in ath_hw_keyreset()
47 if (entry >= common->keymax) { in ath_hw_keyreset()
73 if (common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED) { in ath_hw_keyreset()
91 void *ah = common->ah; in ath_hw_keysetmac()
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/input/
H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd-src/sys/dev/ixgbe/
H A Dif_fdir.c3 Copyright (c) 2001-2017, Intel Corporation
43 if (!(sc->feat_en & IXGBE_FEATURE_FDIR)) in ixgbe_init_fdir()
46 sc->hw.mac.ops.setup_rxpba(&sc->hw, 0, hdrm, in ixgbe_init_fdir()
48 ixgbe_init_fdir_signature_82599(&sc->hw, fdir_pballoc); in ixgbe_init_fdir()
58 if (!(sc->feat_en & IXGBE_FEATURE_FDIR)) in ixgbe_reinit_fdir()
60 if (sc->fdir_reinit != 1) /* Shouldn't happen */ in ixgbe_reinit_fdir()
62 ixgbe_reinit_fdir_tables_82599(&sc->hw); in ixgbe_reinit_fdir()
63 sc->fdir_reinit = 0; in ixgbe_reinit_fdir()
64 /* re-enabl in ixgbe_reinit_fdir()
[all...]

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