| /freebsd-src/sys/contrib/device-tree/Bindings/clock/ |
| H A D | exynos5260-clock.txt | 1 * Samsung Exynos5260 Clock Controller
3 Exynos5260 has 13 clock controllers which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos5260-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
21 - "xrtcxti" - input clock from XRTCXTI
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| H A D | exynos7-clock.txt | 1 * Samsung Exynos7 Clock Controller
3 Exynos7 clock controller has various blocks which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos7-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
22 Required Properties for Clock Controller:
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| H A D | exynos5433-clock.txt | 1 * Samsung Exynos5433 CMU (Clock Management Units)
3 The Exynos5433 clock controller generates and supplies clock to various
8 - compatible: should be one of the following.
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
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| H A D | cirrus,lochnagar.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/cirru
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| H A D | imx8m-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8m-clock.yaml#
5 $schema: http://devicetree.org/meta-schema
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| H A D | amlogic,s4-peripherals-clkc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
4 ---
5 $id: http://devicetree.org/schemas/clock/amlogic,s4-peripherals-clkc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic S4 Peripherals Clock Controller
11 - Yu Tu <yu.tu@amlogic.com>
15 const: amlogic,s4-peripherals-clkc
23 - description: input fixed pll div2
24 - description: input fixed pll div2p5
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| H A D | marvell,berlin.txt | 1 Device Tree Clock bindings for Marvell Berlin
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7 Clock related registers are spread among the chip control registers. Berlin
8 clock node should be a sub-node of the chip controller node. Marvell Berlin2
13 - compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk"
14 - #clock-cells: must be 1
15 - clocks: must be the input parent clock phandle
16 - clock-names: name of the input parent clock
17 Allowed clock-names for the reference clocks are
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| H A D | qoriq-clock.txt | 1 * Clock Block on Freescale QorIQ Platforms
3 Freescale QorIQ chips take primary clocking input from the external
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
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| H A D | xlnx,zynqmp-clk.txt | 1 --------------------------------------------------------------------------
2 Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
4 --------------------------------------------------------------------------
5 The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
6 tree. It reads required input clock frequencies from the devicetree and acts
7 as clock provider for all clock consumers of PS clocks.
9 See clock_bindings.txt for more information on the generic clock bindings.
12 - #clock-cells: Must be 1
13 - compatible: Must contain: "xlnx,zynqmp-clk"
14 - clocks: List of clock specifiers which are external input
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| H A D | renesas,emev2-smu.txt | 1 Device tree Clock bindings for Renesas EMMA Mobile EV2
3 This binding uses the common clock binding.
7 This is not a clock provider, but clocks under SMU depend on it.
10 - compatible: Should be "renesas,emev2-smu"
11 - reg: Address and Size of SMU registers
14 Function block with an input mux and a divider, which corresponds to
15 "Serial clock generator" in fig."Clock System Overview" of the manual,
17 This makes internal (neither input nor output) clock that is provided
18 to input of xxxGCLK block.
21 - compatible: Should be "renesas,emev2-smu-clkdiv"
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| H A D | amlogic,a1-peripherals-clkc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/amlogi
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| H A D | snps,pll-clock.txt | 1 Binding for the AXS10X Generic PLL clock
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible: should be "snps,axs10x-<name>-pll-clock"
9 "snps,axs10x-arc-pll-clock"
10 "snps,axs10x-pgu-pll-clock"
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
14 - #clock-cells: from common clock binding; Should always be set to 0.
17 input-clk: input-clk {
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| H A D | imx8mp-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8mp-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8M Plus Clock Control Module Binding
10 - Anson Huang <Anson.Huang@nxp.com>
13 NXP i.MX8M Plus clock control module is an integrated clock controller, which
18 const: fsl,imx8mp-ccm
25 - description: 32k osc
26 - description: 24m osc
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| H A D | imx8mn-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8mn-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8M Nano Clock Control Module Binding
10 - Anson Huang <Anson.Huang@nxp.com>
13 NXP i.MX8M Nano clock control module is an integrated clock controller, which
18 const: fsl,imx8mn-ccm
25 - description: 32k osc
26 - description: 24m osc
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| H A D | imx8mm-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8mm-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8M Mini Clock Control Module Binding
10 - Anson Huang <Anson.Huang@nxp.com>
13 NXP i.MX8M Mini clock control module is an integrated clock controller, which
18 const: fsl,imx8mm-ccm
25 - description: 32k osc
26 - description: 24m osc
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| /freebsd-src/sys/contrib/device-tree/Bindings/display/ |
| H A D | renesas,du.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Display Unit (DU)
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the Display Unit embedded in the Renesas R-Car
14 Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,du-r8a7742 # for RZ/G1H compatible DU
20 - renesas,du-r8a7743 # for RZ/G1M compatible DU
21 - renesas,du-r8a7744 # for RZ/G1N compatible DU
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| /freebsd-src/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | adi,adv7511.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
15 space conversion, S/PDIF, CEC and HDCP. The transmitter input is
21 - adi,adv7511
22 - adi,adv7511w
23 - adi,adv7513
37 reg-names:
40 needing a non-default address.
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| H A D | adi,adv7511.txt | 2 ------------------------------------------------
6 conversion, S/PDIF, CEC and HDCP. ADV7533/5 supports the DSI interface for input
11 - compatible: Should be one of:
18 - reg: I2C slave addresses
26 The ADV7511 supports a large number of input data formats that differ by their
27 color depth, color format, clock mode, bit justification and random
29 properties describe the input and map directly to the video input tables of the
32 - adi,input-depth: Number of bits per color component at the input (8, 10 or
34 - adi,input-colorspace: The input color space, one of "rgb", "yuv422" or
36 - adi,input-clock: The input clock type, one of "1x" (one clock cycle per
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| /freebsd-src/sys/contrib/device-tree/src/arm/samsung/ |
| H A D | exynos4412-midas.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
12 /dts-v1/;
14 #include "exynos4412-ppmu-common.dtsi"
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/clock/maxim,max77686.h>
20 #include "exynos-pinctrl.h"
34 stdout-path = &serial_2;
38 compatible = "samsung,secure-firmware";
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| /freebsd-src/sys/contrib/device-tree/Bindings/media/ |
| H A D | samsung-fimc.txt | 2 ----------------------------------------------
4 The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices
6 the S5P SoCs series known as CAMIF), MIPI CSIS, FIMC-LITE and FIMC-IS (ISP).
8 The sub-subdevices are defined as child nodes of the common 'camera' node which
10 any single sub-device, like common camera port pins or the CAMCLK clock outputs
14 --------------------
18 - compatible: must be "samsung,fimc", "simple-bus"
19 - clocks: list of clock specifiers, corresponding to entries in
20 the clock-names property;
21 - clock-names : must contain "sclk_cam0", "sclk_cam1", "pxl_async0",
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| H A D | samsung,exynos4210-fimc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,exynos4210-fim
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| /freebsd-src/sys/contrib/device-tree/Bindings/phy/ |
| H A D | ti,phy-am654-serdes.txt | 4 - compatible: Should be "ti,phy-am654-serdes"
5 - reg : Address and length of the register set for the device.
6 - #phy-cells: determine the number of cells that should be given in the
9 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes
12 0 - USB3
13 1 - PCIe0 Lane0
14 2 - ICSS2 SGMII Lane0
16 0 - PCIe1 Lane0
17 1 - PCIe0 Lane1
18 2 - ICSS2 SGMII Lane1
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| /freebsd-src/sys/contrib/device-tree/src/riscv/starfive/ |
| H A D | jh7110-starfive-visionfive-2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-common.dtsi"
17 phy-handle = <&phy1>;
18 phy-mode = "rgmii-id";
22 #address-cells = <1>;
23 #size-cell
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| /freebsd-src/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | rk808.txt | 11 - compatible: "rockchip,rk805"
12 - compatible: "rockchip,rk808"
13 - compatible: "rockchip,rk809"
14 - compatible: "rockchip,rk817"
15 - compatible: "rockchip,rk818"
16 - reg: I2C slave address
17 - interrupts: the interrupt outputs of the controller.
18 - #clock-cells: from common clock binding; shall be set to 1 (multiple clock
19 outputs). See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
22 - clock-output-names: From common clock binding to override the
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| /freebsd-src/sys/contrib/device-tree/Bindings/net/pcs/ |
| H A D | renesas,rzn1-miic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clément Léger <clement.leger@bootlin.com>
17 '#address-cells':
20 '#size-cells':
25 - enum:
26 - renesas,r9a06g032-miic
27 - const: renesas,rzn1-miic
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