| /freebsd-src/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | imx8-ss-dma.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/dma/fsl-edma.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
11 dma_ipg_clk: clock-dm
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| H A D | imx8-ss-lsio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 lsio_bus_clk: clock-lsio-bus {
11 compatible = "fixed-cloc
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| H A D | imx8qm-ss-dma.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
8 uart4_lpcg: clock-controller@5a4a0000 {
9 compatible = "fsl,imx8qxp-lpcg";
11 #clock-cells = <1>;
12 clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
14 clock-indice
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| H A D | imx8qxp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-binding
219 clk: clock-controller { global() label
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| H A D | imx8-ss-conn.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 conn_axi_clk: clock-conn-axi {
11 compatible = "fixed-cloc
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| H A D | imx8dxl-ss-conn.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
6 /delete-node/ &enet1_lpcg;
7 /delete-node/ &fec2;
10 conn_enet0_root_clk: clock-conn-enet0-root {
11 compatible = "fixed-clock";
12 #clock-cell
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| H A D | imx8dxl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/clock/imx8-lpcg.h>
9 #include <dt-binding
129 clk: clock-controller { global() label
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| H A D | imx8qxp-ai_ml.dts | 1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
9 #include "imx8qxp.dtsi"
13 compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
22 stdout-path = &lpuart2;
31 compatible = "gpio-leds";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_leds>;
35 user-led1 {
38 linux,default-trigger = "heartbeat";
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|
| H A D | imx8qxp-mek.dts | 1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
8 #include "imx8qxp.dtsi"
9 #include <dt-bindings/usb/pd.h>
13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
16 stdout-pat
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| H A D | imx8qm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controlle
282 clk: clock-controller { global() label
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| /freebsd-src/sys/contrib/device-tree/Bindings/arm/freescale/ |
| H A D | fsl,scu.txt | 2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
31 be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
63 Client nodes are maintained as children of the relevant IMX-SCU device node.
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|
| /freebsd-src/sys/contrib/device-tree/Bindings/clock/ |
| H A D | fsl,scu-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX SCU Client Device Node - Clock Controller Based on SCU Message Protocol
10 - Abel Vesa <abel.vesa@nxp.com>
13 Client nodes are maintained as children of the relevant IMX-SCU device node.
15 (Documentation/devicetree/bindings/clock/clock-bindings.txt)
18 include/dt-bindings/clock/imx8qxp-clock.h
23 - enum:
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|
| /freebsd-src/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | nxp,imx8qxp-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP IMX8QXP ADC
10 - Cai Huoqing <caihuoqing@baidu.com>
13 Supports the ADC found on the IMX8QXP SoC.
17 const: nxp,imx8qxp-adc
28 clock-names:
30 - const: per
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|
| /freebsd-src/sys/contrib/device-tree/Bindings/firmware/ |
| H A D | fsl,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
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|
| /freebsd-src/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | fsl,imx8qxp-csr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
17 use-case is for some other nodes to acquire a reference to the syscon node
18 by phandle, and the other typical use-case is that the operating system
23 pattern: "^syscon@[0-9a-f]+$"
27 - enum:
28 - fsl,imx8qxp-mipi-lvds-csr
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|
| /freebsd-src/sys/contrib/device-tree/Bindings/bus/ |
| H A D | fsl,imx8qxp-pixel-link-msi-bus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
35 - $ref: simple-pm-bus.yaml#
37 # We need a select here so we don't match all nodes with 'simple-pm-bus'.
43 - fsl,imx8qxp-display-pixel-link-msi-bus
44 - fsl,imx8qm-display-pixel-link-msi-bus
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|
| /freebsd-src/sys/contrib/device-tree/Bindings/phy/ |
| H A D | mixel,mipi-dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
23 - fsl,imx8mq-mipi-dphy
24 - fsl,imx8qxp-mipi-dphy
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|
| /freebsd-src/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | fsl,imx8qxp-ldb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
41 - fsl,imx8qm-ldb
42 - fsl,imx8qxp-ldb
44 "#address-cells":
47 "#size-cells":
52 - description: pixel clock
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|
| /freebsd-src/sys/contrib/device-tree/Bindings/sound/ |
| H A D | fsl,asrc.txt | 11 - compatible : Compatible list, should contain one of the following
13 "fsl,imx35-asrc",
14 "fsl,imx53-asrc",
15 "fsl,imx8qm-asrc",
16 "fsl,imx8qxp-asrc",
18 - reg : Offset and length of the register set for the device.
20 - interrupts : Contains the spdif interrupt.
22 - dmas : Generic dma devicetree binding as described in
25 - dma-names : Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc".
27 - clocks : Contains an entry for each entry in clock-names.
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|
| H A D | fsl,mqs.txt | 4 - compatible : Must contain one of "fsl,imx6sx-mqs", "fsl,codec-mqs"
5 "fsl,imx8qm-mqs", "fsl,imx8qxp-mqs", "fsl,imx93-mqs".
6 - clocks : A list of phandles + clock-specifiers, one for each entry in
7 clock-names
8 - clock-names : "mclk" - must required.
9 "core" - required if compatible is "fsl,imx8qm-mqs", it
11 - gpr : A phandle of General Purpose Registers in IOMUX Controller.
12 Required if compatible is "fsl,imx6sx-mqs".
14 Required if compatible is "fsl,imx8qm-mqs":
15 - power-domains: A phandle of PM domain provider node.
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|
| /freebsd-src/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-fsl-lpspi.txt | 4 - compatible :
5 - "fsl,imx7ulp-spi" for LPSPI compatible with the one integrated on i.MX7ULP soc
6 - "fsl,imx8qxp-spi" for LPSPI compatible with the one integrated on i.MX8QXP soc
7 - reg : address and length of the lpspi master registers
8 - interrupt-parent : core interrupt controller
9 - interrupts : lpspi interrupt
10 - clocks : lpspi clock specifier. Its number and order need to correspond to the
11 value in clock-names.
12 - clock-names : Corresponding to per clock and ipg clock in "clocks"
13 respectively. In i.MX7ULP, it only has per clk, so use CLK_DUMMY
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|
| /freebsd-src/sys/contrib/device-tree/Bindings/remoteproc/ |
| H A D | fsl,imx-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/fsl,imx-rproc.yaml#
5 $schema: http://devicetree.org/meta-schema
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