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/freebsd-src/sys/contrib/device-tree/Bindings/display/samsung/
H A Dsamsung,exynos-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC HDMI
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-hdmi
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/exynos/
H A Dexynos_hdmi.txt1 Device-Tree bindings for drm hdmi driver
4 - compatible: value should be one among the following:
5 1) "samsung,exynos4210-hdmi"
6 2) "samsung,exynos4212-hdmi"
7 3) "samsung,exynos5420-hdmi"
8 4) "samsung,exynos5433-hdmi"
9 - reg: physical base address of the hdmi and length of memory mapped
11 - interrupts: interrupt number to the cpu.
12 - hpd-gpios: following information about the hotplug gpio pin.
13 a) phandle of the gpio controller node.
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/media/
H A Ds5p-cec.txt1 * Samsung HDMI CEC driver
3 The HDMI CEC module is present is Samsung SoCs and its purpose is to
4 handle communication between HDMI connected devices over the CEC bus.
7 - compatible : value should be following
8 "samsung,s5p-cec"
10 - reg : Physical base address of the IP registers and length of memory
13 - interrupts : HDMI CEC interrupt number to the CPU.
14 - clocks : from common clock binding: handle to HDMI CEC clock.
15 - clock-names : from common clock binding: must contain "hdmicec",
17 - samsung,syscon-phandle - phandle to the PMU system controller
[all …]
H A Dstih-cec.txt1 STMicroelectronics STIH4xx HDMI CEC driver
4 - compatible : value should be "st,stih-cec"
5 - reg : Physical base address of the IP registers and length of memory
7 - clocks : from common clock binding: handle to HDMI CEC clock
8 - interrupts : HDMI CEC interrupt number to the CPU.
9 - pinctrl-names: Contains only one value - "default"
10 - pinctrl-0: Specifies the pin control groups used for CEC hardware.
11 - resets: Reference to a reset controller
12 - hdmi-phandle: Phandle to the HDMI controller, see also cec.txt.
16 sti-cec@94a087c {
[all …]
H A Damlogic,meson-gx-ao-cec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/media/amlogic,meson-gx-ao-cec.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson AO-CEC Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic Meson AO-CEC module is present is Amlogic SoCs and its purpose is
15 to handle communication between HDMI connected devices over the CEC bus.
20 - amlogic,meson-gx-ao-cec # GXBB, GXL, GXM, G12A and SM1 AO_CEC_A module
21 - amlogic,meson-g12a-ao-cec # G12A AO_CEC_B module
[all …]
H A Dtegra-cec.txt1 * Tegra HDMI CEC hardware
3 The HDMI CEC module is present in Tegra SoCs and its purpose is to
4 handle communication between HDMI connected devices over the CEC bus.
7 - compatible : value should be one of the following:
8 "nvidia,tegra114-cec"
9 "nvidia,tegra124-cec"
10 "nvidia,tegra210-cec"
11 - reg : Physical base address of the IP registers and length of memory
13 - interrupts : HDMI CEC interrupt number to the CPU.
14 - clocks : from common clock binding: handle to HDMI CEC clock.
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra HDMI Output Encoder
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^hdmi@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-hdmi
[all …]
H A Dnvidia,tegra124-sor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP
19 pattern: "^sor@[0-9a-f]+$"
23 - enum:
24 - nvidia,tegra124-sor
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/msm/
H A Dhdmi.txt1 Qualcomm adreno/snapdragon hdmi output
4 - compatible: one of the following
5 * "qcom,hdmi-tx-8996"
6 * "qcom,hdmi-tx-8994"
7 * "qcom,hdmi-tx-8084"
8 * "qcom,hdmi-tx-8974"
9 * "qcom,hdmi-tx-8660"
10 * "qcom,hdmi-tx-8960"
11 - reg: Physical base address and length of the controller's registers
12 - reg-names: "core_physical"
[all …]
H A Dhdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/display/msm/hdmi
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/sound/
H A Drockchip-max98090.txt4 - compatible: "rockchip,rockchip-audio-max98090"
5 - rockchip,model: The user-visible name of this sound complex
6 - rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
10 - rockchip,audio-codec: The phandle of the MAX98090 audio codec.
11 - rockchip,headset-codec: The phandle of Ext chip for jack detection. This is
12 required if there is rockchip,audio-codec.
13 - rockchip,hdmi-codec: The phandle of HDMI device for HDMI codec.
17 /* For max98090-only board. */
19 compatible = "rockchip,rockchip-audio-max98090";
20 rockchip,model = "ROCKCHIP-I2S";
[all …]
H A Dimx-audio-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/imx-audio-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX audio complex with HDMI
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
15 - fsl,imx-audio-hdmi
16 - fsl,imx-audio-sii902x
22 audio-cpu:
23 $ref: /schemas/types.yaml#/definitions/phandle
[all …]
H A Dsamsung,snow.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
16 - google,snow-audio-max98090
17 - google,snow-audio-max98091
18 - google,snow-audio-max98095
24 sound-dai:
25 description: List of phandles to the CODEC and HDMI IP nodes.
[all …]
H A Drockchip,rk3288-hdmi-analog.txt1 ROCKCHIP RK3288 with HDMI and analog audio
4 - compatible: "rockchip,rk3288-hdmi-analog"
5 - rockchip,model: The user-visible name of this sound complex
6 - rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
8 - rockchip,audio-codec: The phandle of the analog audio codec.
9 - rockchip,routing: A list of the connections between audio components.
16 - rockchip,hp-en-gpios = The phandle of the GPIO that power up/down the
18 - rockchip,hp-det-gpios = The phandle of the GPIO that detects the headphone
20 - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt
25 compatible = "rockchip,rk3288-hdmi-analog";
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/imx/
H A Dfsl,imx6-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdm
[all...]
H A Dhdmi.txt1 Freescale i.MX6 DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
9 following device-specific properties.
14 - compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
15 - reg: See dw_hdmi.txt.
16 - interrupts: HDMI interrupt number
17 - clocks: See dw_hdmi.txt.
18 - clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
19 - ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/rockchip/
H A Drockchip,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdm
[all...]
H A Ddw_hdmi-rockchip.txt1 Rockchip DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
9 following device-specific properties.
14 - compatible: should be one of the following:
15 "rockchip,rk3228-dw-hdmi"
16 "rockchip,rk3288-dw-hdmi"
17 "rockchip,rk3328-dw-hdmi"
18 "rockchip,rk3399-dw-hdmi"
19 - reg: See dw_hdmi.txt.
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/media/cec/
H A Dsamsung,s5p-cec.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/cec/samsung,s5p-cec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5PV210 and Exynos HDMI CEC
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
14 - $ref: cec-common.yaml#
18 const: samsung,s5p-cec
23 clock-names:
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/phy/
H A Dphy-rockchip-inno-hdmi.txt1 ROCKCHIP HDMI PHY WITH INNO IP BLOCK
4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rk3228-hdmi-phy",
6 * "rockchip,rk3328-hdmi-phy";
7 - reg : Address and length of the hdmi phy control register set
8 - clocks : phandle + clock specifier for the phy clocks
9 - clock-names : string, clock name, must contain "sysclk" for system
10 control and register configuration, "refoclk" for crystal-
11 oscillator reference PLL clock input and "refpclk" for pclk-
13 - #clock-cells: should be 0.
[all …]
H A Dqcom,hdmi-phy-other.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-other.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm Adreno/Snapdragon HDMI phy
11 - Rob Clark <robdclark@gmail.com>
16 - qcom,hdmi-phy-8660
17 - qcom,hdmi-phy-8960
18 - qcom,hdmi-phy-8974
19 - qcom,hdmi-phy-8084
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/
H A Dzte,vou.txt6 for typical output devices, like HDMI, TV Encoder, VGA, and RGB LCD.
10 It must be the parent node of all the sub-device nodes.
13 - compatible: should be "zte,zx296718-vou"
14 - #address-cells: should be <1>
15 - #size-cells: should be <1>
16 - ranges: list of address translations between VOU and sub-devices
21 - compatible: should be "zte,zx296718-dpc"
22 - reg: Physical base address and length of DPC register regions, one for each
23 entry in 'reg-names'
24 - reg-names: The names of register regions. The following regions are required:
[all …]
H A Dbrcm,bcm2835-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/brcm,bcm2835-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom VC4 (VideoCore4) HDMI Controller
10 - Eric Anholt <eric@anholt.net>
14 const: brcm,bcm2835-hdmi
18 - description: HDMI register range
19 - description: HD register range
26 - description: The pixel clock
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek HDMI Encoder
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
14 The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
20 - mediatek,mt2701-hdmi
21 - mediatek,mt7623-hdmi
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/connector/
H A Dhdmi-connector.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/connector/hdmi-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HDMI Connector
10 - Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
14 const: hdmi-connector
17 description: The HDMI connector type
19 - a # Standard full size
20 - b # Never deployed?
[all …]

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