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/freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dst,stih407-irq-syscfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
15 Configuration registers. This device is used to unmask them prior to use.
19 const: st,stih407-irq-syscfg
22 description: Phandle to Cortex-A9 IRQ system config registers
25 st,irq-device:
27 $ref: /schemas/types.yaml#/definitions/uint32-array
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H A Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controlle
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H A Dapple,aic2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
21 - Software triggering (ORed with hw line)
22 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
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H A Dst,sti-irq-syscfg.txt2 -----------------------------------------------------------
9 - compatible : Should be "st,stih407-irq-syscfg"
10 - st,syscfg : Phandle to Cortex-A9 IRQ system config registers
11 - st,irq-device : Array of IRQs to enable - should be 2 in length
12 - st,fiq-device : Array of FIQs to enable - should be 2 in length
15 - st,invert-ext : External IRQs can be inverted at will. This property inverts
23 irq-syscfg {
24 compatible = "st,stih407-irq-syscfg";
26 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
28 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
/freebsd-src/sys/contrib/device-tree/Bindings/sound/
H A Dfsl,ssi.txt3 The SSI is a serial device that communicates with audio codecs. It can
4 be programmed in AC97, I2S, left-justified, or right-justified modes.
7 - compatible: Compatible list, should contain one of the following
9 fsl,mpc8610-ssi
10 fsl,imx51-ssi
11 fsl,imx35-ssi
12 fsl,imx21-ssi
13 - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
14 - reg: Offset and length of the register set for the device.
15 - interrupts: <a b> where a is the interrupt number and b is a
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/freebsd-src/sys/arm/arm/
H A Dlocore.S1 /*-
2 * Copyright 2004-2014 Olivier Houchard <cognet@FreeBSD.org>
3 * Copyright 2012-2014 Ian Lepore <ian@FreeBSD.org>
4 * Copyright 2013-2014 Andrew Turner <andrew@FreeBSD.org>
51 /* A small statically-allocated stack used only during initarm() and AP startup. */
71 /* Ensure that IRQ, FIQ and Aborts will be disabled after eret */ ;\
82 mov r0, -1 ;\
89 * r0 - metadata pointer or 0
90 * r1 - if (r0 == 0) then metadata pointer
92 * r0 -
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/freebsd-src/sys/contrib/alpine-hal/
H A Dal_hal_nb_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
480 /* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity
485 /* Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity
512 By default, CPU0 only exits poreset when the CPUs cluster exits power-on-reset and then kicks other…
513 …t by primary CPU as part of the initialization process will initiate power-on-reset to this specif…
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/freebsd-src/sys/contrib/device-tree/src/arm/st/
H A Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-reset
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/freebsd-src/contrib/llvm-project/clang/include/clang/Basic/
H A DAttrDocs.td1 //==--- AttrDocs.td - Attribute documentation ------
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H A DAttr.td1 //==--- Attr.td - attribute definitions ------
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