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/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXTargetStreamer.cpp49 static bool isDwarfSection(const MCObjectFileInfo *FI, in isDwarfSection()
55 return Section == FI->getDwarfAbbrevSection() || in isDwarfSection()
56 Section == FI->getDwarfInfoSection() || in isDwarfSection()
57 Section == FI->getDwarfMacinfoSection() || in isDwarfSection()
58 Section == FI->getDwarfFrameSection() || in isDwarfSection()
59 Section == FI->getDwarfAddrSection() || in isDwarfSection()
60 Section == FI->getDwarfRangesSection() || in isDwarfSection()
61 Section == FI->getDwarfARangesSection() || in isDwarfSection()
62 Section == FI->getDwarfLocSection() || in isDwarfSection()
63 Section == FI in isDwarfSection()
45 isDwarfSection(const MCObjectFileInfo * FI,const MCSection * Section) isDwarfSection() argument
89 const MCObjectFileInfo *FI = getStreamer().getContext().getObjectFileInfo(); changeSection() local
[all...]
/llvm-project/llvm/test/MC/AMDGPU/
H A Dgfx12_asm_vopcx_dpp8.s8 v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
9 // GFX12: v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
14 v_cmpx_class_f16 v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
15 // GFX12: v_cmpx_class_f16 v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfb,0x7d,0x81,0x77,0x39,0x05]
17 v_cmpx_class_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
23 v_cmpx_class_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
24 // GFX12: v_cmpx_class_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfc,0x7d,0x01,0x77,0x39,0x05]
26 v_cmpx_class_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
32 v_cmpx_eq_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
33 // GFX12: v_cmpx_eq_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi
[all...]
H A Dgfx11_asm_vopcx_dpp8.s8 v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
9 // GFX11: v_cmpx_class_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfa,0x7d,0x01,0x77,0x39,0x05]
17 v_cmpx_class_f16 v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
18 // GFX11: v_cmpx_class_f16 v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfb,0x7d,0x81,0x77,0x39,0x05]
20 v_cmpx_class_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
26 v_cmpx_class_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
27 // GFX11: v_cmpx_class_f32 v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0xfc,0x7d,0x01,0x77,0x39,0x05]
29 v_cmpx_class_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
35 v_cmpx_eq_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
36 // GFX11: v_cmpx_eq_f16 v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi
[all...]
H A Dgfx12_asm_vop3cx_dpp8.s8 v_cmpx_class_f16_e64_dpp v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
9 // GFX12: v_cmpx_class_f16_e64_dpp v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
11 v_cmpx_class_f16_e64_dpp v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] fi:1
12 // GFX12: v_cmpx_class_f16_e64_dpp v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xea,0x04,0x00,0x00,0x01,0x77,0x39,0x05]
14 v_cmpx_class_f16_e64_dpp v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] fi:1
15 // GFX12: v_cmpx_class_f16_e64_dpp v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xea,0xe8,0x01,0x00,0x01,0x77,0x39,0x05]
17 v_cmpx_class_f16_e64_dpp -|v255.l|, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:0
23 v_cmpx_class_f16_e64_dpp v1.h, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
24 // GFX12: v_cmpx_class_f16_e64_dpp v1.h, v2.l op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x08,0xfd,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
26 v_cmpx_class_f16_e64_dpp -|v255.l|, v255.h dpp8:[0,0,0,0,0,0,0,0] fi
[all...]
H A Dgfx11_asm_vop1_dpp8.s8 v_bfrev_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
9 // GFX11: v_bfrev_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05]
11 v_bfrev_b32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
20 v_ceil_f16 v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] fi:1
21 // GFX11: v_ceil_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xb8,0x0a,0x7f,0x81,0x77,0x39,0x05]
23 v_ceil_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
29 v_ceil_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
30 // GFX11: v_ceil_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x44,0x0a,0x7e,0x01,0x77,0x39,0x05]
32 v_ceil_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
38 v_cls_i32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi
[all...]
H A Dgfx12_asm_vop1_dpp8.s10 v_bfrev_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
11 // GFX12: v_bfrev_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05]
13 v_bfrev_b32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
19 v_ceil_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
20 // GFX12: v_ceil_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xb8,0x0a,0x7e,0x01,0x77,0x39,0x05]
22 v_ceil_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
28 v_ceil_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
29 // GFX12: v_ceil_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x44,0x0a,0x7e,0x01,0x77,0x39,0x05]
31 v_ceil_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
37 v_cls_i32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi
[all...]
H A Dgfx12_asm_vop2_dpp8.s11 v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1
12 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
15 v_add_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:0
23 v_add_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1
24 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
27 v_add_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0
34 v_add_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
35 // GFX12: v_add_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x64,0x01,0x77,0x39,0x05]
37 v_add_f16 v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:0
40 v_add_f16 v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi
[all...]
H A Dgfx11_asm_vop2_dpp8.s11 v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1
12 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
15 v_add_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:0
23 v_add_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1
24 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
27 v_add_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0
34 v_add_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
35 // GFX11: v_add_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x64,0x01,0x77,0x39,0x05]
43 v_add_f16 v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
44 // GFX11: v_add_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi
[all...]
H A Dgfx11_asm_vop3_dpp8_from_vop1.s7 v_bfrev_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
8 // GFX11: v_bfrev_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x00,0xb8,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
10 v_bfrev_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
22 v_ceil_f16_e64_dpp v5.l, v1.l mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
23 // GFX11: v_ceil_f16_e64_dpp v5.l, v1.l mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x00,0xdc,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
25 v_ceil_f16_e64_dpp v5.l, v1.h mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
26 // GFX11: v_ceil_f16_e64_dpp v5.l, v1.h op_sel:[1,0] mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x08,0xdc,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
28 v_ceil_f16_e64_dpp v255.l, -|v255.l| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
31 v_ceil_f16_e64_dpp v255.h, -|v255.l| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
40 v_ceil_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi
[all...]
H A Dgfx11_asm_vop3_dpp8_from_vopcx.s8 v_cmpx_class_f16_e64_dpp v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
9 // GFX11: v_cmpx_class_f16_e64_dpp v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x00,0xfd,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
11 v_cmpx_class_f16_e64_dpp -|v255.l|, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:0
17 v_cmpx_class_f16_e64_dpp v1.h, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
18 // GFX11: v_cmpx_class_f16_e64_dpp v1.h, v2.l op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x08,0xfd,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
20 v_cmpx_class_f16_e64_dpp -|v255.l|, v255.h dpp8:[0,0,0,0,0,0,0,0] fi:0
26 v_cmpx_class_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
27 // GFX11: v_cmpx_class_f32_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x7e,0x00,0xfe,0xd4,0xea,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
29 v_cmpx_class_f32_e64_dpp -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
38 v_cmpx_eq_f16_e64_dpp -v1.l, |v2.l| dpp8:[7,6,5,4,3,2,1,0] fi
[all...]
H A Dgfx10_asm_dpp8.s255 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:0
258 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
261 v_cvt_f32_i32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
264 v_cvt_f32_u32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
267 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
270 v_cvt_i32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
273 v_cvt_f16_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
276 v_cvt_f32_f16_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
279 v_cvt_rpi_i32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
282 v_cvt_flr_i32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi
[all...]
H A Dgfx12_asm_vop3_from_vop1_dpp8.s7 v_bfrev_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
8 // GFX12: v_bfrev_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x00,0xb8,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
10 v_bfrev_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
19 v_ceil_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
20 // GFX12: v_ceil_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x00,0xdc,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
22 v_ceil_f16_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
31 v_ceil_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
32 // GFX12: v_ceil_f32_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x00,0xa2,0xd5,0xea,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
34 v_ceil_f32_e64_dpp v255, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
40 v_cls_i32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi
[all...]
H A Dgfx10_asm_dpp16.s372 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:0
375 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
378 v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
381 v_cvt_f32_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
384 v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
387 v_cvt_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
390 v_cvt_f16_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
393 v_cvt_f32_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
396 v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
399 v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi
[all...]
/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopFlatten.cpp468 static bool checkPHIs(FlattenInfo &FI, const TargetTransformInfo *TTI) { in checkPHIs() argument
484 SafeOuterPHIs.insert(FI.OuterInductionPHI); in checkPHIs()
488 for (PHINode &InnerPHI : FI.InnerLoop->getHeader()->phis()) { in checkPHIs()
491 if (&InnerPHI == FI.InnerInductionPHI) in checkPHIs()
493 if (FI.isNarrowInductionPhi(&InnerPHI)) in checkPHIs()
500 InnerPHI.getIncomingValueForBlock(FI.InnerLoop->getLoopPreheader()); in checkPHIs()
502 InnerPHI.getIncomingValueForBlock(FI.InnerLoop->getLoopLatch()); in checkPHIs()
508 if (!OuterPHI || OuterPHI->getParent() != FI.OuterLoop->getHeader()) { in checkPHIs()
518 OuterPHI->getIncomingValueForBlock(FI.OuterLoop->getLoopLatch())); in checkPHIs()
536 FI in checkPHIs()
553 checkOuterLoopInsts(FlattenInfo & FI,SmallPtrSetImpl<Instruction * > & IterationInstructions,const TargetTransformInfo * TTI) checkOuterLoopInsts() argument
620 checkIVUsers(FlattenInfo & FI) checkIVUsers() argument
644 checkOverflow(FlattenInfo & FI,DominatorTree * DT,AssumptionCache * AC) checkOverflow() argument
701 CanFlattenLoopPair(FlattenInfo & FI,DominatorTree * DT,LoopInfo * LI,ScalarEvolution * SE,AssumptionCache * AC,const TargetTransformInfo * TTI) CanFlattenLoopPair() argument
747 DoFlattenLoopPair(FlattenInfo & FI,DominatorTree * DT,LoopInfo * LI,ScalarEvolution * SE,AssumptionCache * AC,const TargetTransformInfo * TTI,LPMUpdater * U,MemorySSAUpdater * MSSAU) DoFlattenLoopPair() argument
838 CanWidenIV(FlattenInfo & FI,DominatorTree * DT,LoopInfo * LI,ScalarEvolution * SE,AssumptionCache * AC,const TargetTransformInfo * TTI) CanWidenIV() argument
904 FlattenLoopPair(FlattenInfo & FI,DominatorTree * DT,LoopInfo * LI,ScalarEvolution * SE,AssumptionCache * AC,const TargetTransformInfo * TTI,LPMUpdater * U,MemorySSAUpdater * MSSAU,const LoopAccessInfo & LAI) FlattenLoopPair() argument
1017 FlattenInfo FI(OuterLoop, InnerLoop); run() local
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/llvm-project/bolt/utils/
H A Dbughunter.sh67 fi
72 fi
76 fi
80 fi
84 fi
88 fi
103 fi
107 fi
112 fi
113 fi
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/llvm-project/llvm/utils/release/
H A Dtest-release.sh20 fi
57 fi
131 fi
223 fi
229 fi
233 fi
236 fi
240 fi
246 fi
250 fi
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/llvm-project/compiler-rt/lib/asan/scripts/
H A Dasan_device_setup44 fi
57 fi
58 fi
66 fi
72 fi
87 fi
106 fi
121 fi
129 fi
137 fi
[all …]
/llvm-project/llvm/test/CodeGen/SystemZ/
H A Dframe-27.mir20 # CHECK: alloc FI(1) at SP[-4255]
21 # CHECK-NEXT: alloc FI(0) at SP[-4271]
22 # CHECK-NEXT: alloc FI(2) at SP[-4280]
23 # CHECK-NEXT: alloc FI(3) at SP[-4288]
43 # CHECK: alloc FI(0) at SP[-176]
44 # CHECK-NEXT: alloc FI(1) at SP[-4271]
45 # CHECK-NEXT: alloc FI(2) at SP[-4280]
46 # CHECK-NEXT: alloc FI(3) at SP[-4288]
66 # CHECK: alloc FI(1) at SP[-8350]
67 # CHECK-NEXT: alloc FI(0) at SP[-12445]
[all …]
/llvm-project/llvm/lib/CodeGen/
H A DMIRYamlMapping.cpp22 FrameIndex::FrameIndex(int FI, const llvm::MachineFrameInfo &MFI) { in FrameIndex() argument
23 IsFixed = MFI.isFixedObjectIndex(FI); in FrameIndex()
25 FI -= MFI.getObjectIndexBegin(); in FrameIndex()
26 this->FI = FI; in FrameIndex()
31 int FI = this->FI; in getFI() local
33 if (unsigned(FI) >= MFI.getNumFixedObjects()) in getFI() local
35 formatv("invalid fixed frame index {0}", FI).str(), in getFI()
37 FI += MFI.getObjectIndexBegin(); in getFI()
39 if (unsigned(FI + MFI.getNumFixedObjects()) >= MFI.getNumObjects()) in getFI()
40 return make_error<StringError>(formatv("invalid frame index {0}", FI).str(), in getFI()
[all …]
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64StackTaggingPreRA.cpp71 void uncheckUsesOf(unsigned TaggedReg, int FI); in AArch64StackTaggingPreRA()
173 void AArch64StackTaggingPreRA::uncheckUsesOf(unsigned TaggedReg, int FI) { in mayUseUncheckedLoadStore()
177 // FI operand is always the one before the immediate offset. in uncheckUsesOf()
181 UseI.getOperand(OpIdx).ChangeToFrameIndex(FI); in uncheckUsesOf()
185 uncheckUsesOf(UseI.getOperand(0).getReg(), FI); in uncheckUsesOf()
193 int FI = I->getOperand(1).getIndex(); in uncheckLoadsAndStores()
194 uncheckUsesOf(TaggedReg, FI); in uncheckLoadsAndStores()
200 int FI;
202 SlotWithTag(int FI, int Tag) : FI(F
176 uncheckUsesOf(unsigned TaggedReg,int FI) uncheckUsesOf() argument
196 int FI = I->getOperand(1).getIndex(); uncheckLoadsAndStores() local
203 int FI; global() member
228 isSlotPreAllocated(MachineFrameInfo * MFI,int FI) isSlotPreAllocated() argument
357 int FI = I.getOperand(1).getIndex(); runOnMachineFunction() local
367 for (int FI : TaggedSlots) runOnMachineFunction() local
384 int FI = I->getOperand(1).getIndex(); runOnMachineFunction() local
[all...]
/llvm-project/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX11.rst1158 …sk<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
1159 …sk<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
1160 …sk<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
1161 …sk<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
1162 …sk<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
1163 …sk<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
1164 …sk<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
1165 …sk<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
1166 …sk<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
1167 …sk<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
[all …]
/llvm-project/clang/test/CodeGenObjC/
H A Dproperty-complex.m26 printf("im0: %.2f + %.2fi\n", __real iv0, __imag iv0);
30 printf("setIm0: %.2f + %.2fi\n", __real a0, __imag a0);
35 printf("p0: %.2f + %.2fi\n", __real iv0, __imag iv0);
39 printf("setP0: %.2f + %.2fi\n", __real a0, __imag a0);
54 printf("l0: %.2f + %.2fi\n", __real l0, __imag l0);
55 printf("l1: %.2f + %.2fi\n", __real l1, __imag l1);
56 printf("l2: %.2f + %.2fi\n", __real l2, __imag l2);
57 printf("l3: %.2f + %.2fi\n", __real l3, __imag l3);
58 printf("l4: %.2f + %.2fi\n", __real l4, __imag l4);
59 printf("l5: %.2f + %.2fi\n", __real l5, __imag l5);
[all …]
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUArgumentUsageInfo.cpp64 for (const auto &FI : ArgInfoMap) { in print()
65 OS << "Arguments for " << FI.first->getName() << '\n' in print() local
66 << " PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer in print()
67 << " DispatchPtr: " << FI.second.DispatchPtr in print()
68 << " QueuePtr: " << FI.second.QueuePtr in print()
69 << " KernargSegmentPtr: " << FI.second.KernargSegmentPtr in print()
70 << " DispatchID: " << FI.second.DispatchID in print()
71 << " FlatScratchInit: " << FI.second.FlatScratchInit in print()
72 << " PrivateSegmentSize: " << FI.second.PrivateSegmentSize in print()
73 << " WorkGroupIDX: " << FI in print()
[all...]
/llvm-project/lldb/scripts/lldb-test-qemu/
H A Drun-qemu.sh64 fi
69 fi
77 fi
83 fi
84 fi
91 fi
96 fi
97 fi
105 fi
108 fi
[all …]
/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx11_dasm_vopc_dpp8.txt14 # W32-REAL16: v_cmp_class_f16 vcc_lo, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00]
15 # W64-REAL16: v_cmp_class_f16 vcc, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00]
16 # W32-FAKE16: v_cmp_class_f16 vcc_lo, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00]
17 # W64-FAKE16: v_cmp_class_f16 vcc, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfa,0x7c,0x7f,0x00,0x00,0x00]
32 # W32-REAL16: v_cmp_class_f16 vcc_lo, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00]
33 # W64-REAL16: v_cmp_class_f16 vcc, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00]
34 # W32-FAKE16: v_cmp_class_f16 vcc_lo, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00]
35 # W64-FAKE16: v_cmp_class_f16 vcc, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/, v255/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfb,0x7c,0xff,0x00,0x00,0x00]
42 # W32: v_cmp_class_f32 vcc_lo, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfd,0x7c,0xff,0x00,0x00,0x00]
43 # W64: v_cmp_class_f32 vcc, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi
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