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/freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmediatek,mtk-cirq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mediatek,mtk-cirq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Youlin Pei <youlin.pei@mediatek.com>
14 work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC.
16 to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
25 - enum:
26 - mediatek,mt2701-cirq
27 - mediatek,mt8135-cirq
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H A Dmediatek,cirq.txt4 work outside MCUSYS which comprises with Cortex-Ax cores,CCI and GIC.
6 to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
12 - compatible: should be one of
13 - "mediatek,mt2701-cirq" for mt2701 CIRQ
14 - "mediatek,mt8135-cirq" for mt8135 CIRQ
15 - "mediatek,mt8173-cirq" for mt8173 CIRQ
17 - interrupt-controller : Identifies the node as an interrupt controller.
18 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
19 - reg: Physical base address of the cirq registers and length of memory
21 - mediatek,ext-irq-range: Identifies external irq number range in different
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/freebsd-src/sys/contrib/device-tree/Bindings/mtd/
H A Dbrcm,brcmnand.txt3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v2.1
24 brcm,brcmnand-v2.2
25 brcm,brcmnand-v4.0
26 brcm,brcmnand-v5.0
27 brcm,brcmnand-v6.0
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/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dti,k3-am654-cpts.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am65
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H A Dti,k3-am654-cpsw-nuss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am65
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/freebsd-src/sys/contrib/device-tree/src/powerpc/
H A Da4m072.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 &gpt0 { fsl,has-wdt; };
15 &gpt3 { gpio-controller; };
16 &gpt4 { gpio-controller; };
17 &gpt5 { gpio-controller; };
24 #address-cells = <1>;
25 #size-cells = <1>;
26 compatible = "fsl,mpc5200b-immr";
29 bus-frequency = <0>; /* From boot loader */
30 system-frequency = <0>; /* From boot loader */
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H A Dcanyonlands.dts4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
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H A Dglacier.dts4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
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/freebsd-src/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm-hr2.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
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H A Dbcm-nsp.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
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H A Dbcm-cygnus.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-cygnus.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
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/freebsd-src/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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/freebsd-src/sys/contrib/dev/athk/ath12k/
H A Dpci.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
38 * 4K - 32 = 0xFE0
53 /* TODO: revisit IRQ mapping for new SRNG's */
68 "mhi-er0",
69 "mhi-er1",
86 "host2wbm-desc-feed",
87 "host2reo-re-injection",
88 "host2reo-command",
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/freebsd-src/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controlle
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H A Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controlle
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H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sra
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H A Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-t
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H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-binding
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/freebsd-src/sys/x86/x86/
H A Dlocal_apic.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
15 * 3. Neither the name of the author nor the names of any co-contributors
98 * I/O interrupts use non-negative IRQ values. These values are used
99 * to mark unused IDT entries or IDT entries reserved for a non-I/O
102 #define IRQ_FREE -
1512 apic_alloc_vector(u_int apic_id,u_int irq) apic_alloc_vector() argument
1637 apic_free_vector(u_int apic_id,u_int vector,u_int irq) apic_free_vector() argument
1678 int irq; apic_idt_to_irq() local
1702 u_int irq; DB_SHOW_COMMAND_FLAGS() local
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/freebsd-src/sys/arm/freescale/imx/
H A Dimx_gpt.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
51 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v))
53 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r))
97 { -1, 0 }
101 {"fsl,imx6dl-gpt", 1},
102 {"fsl,imx6q-gpt", 1},
103 {"fsl,imx6ul-gpt", 1},
104 {"fsl,imx53-gpt", 1},
105 {"fsl,imx51-gpt", 1},
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-binding
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/freebsd-src/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
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/freebsd-src/sys/dev/mlx5/mlx5_en/
H A Dmlx5_en_main.c1 /*-
2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved.
370 struct mlx5_core_dev *mdev = priv->mdev; in mlx5e_update_carrier()
378 bool ext; in mlx5e_update_carrier()
385 priv->media_status_last |= IFM_ACTIVE; in mlx5e_update_carrier()
387 priv->media_status_last &= ~IFM_ACTIVE; in mlx5e_update_carrier()
388 priv->media_active_last = IFM_ETHER; in mlx5e_update_carrier()
389 if_link_state_change(priv->ifp, LINK_STATE_DOWN); in mlx5e_update_carrier()
396 priv->media_active_last = IFM_ETHER; in mlx5e_update_carrier()
397 if_setbaudrate(priv->if in mlx5e_update_carrier()
373 bool ext; mlx5e_update_carrier() local
468 mlx5e_find_link_mode(u32 subtype,bool ext) mlx5e_find_link_mode() argument
541 bool ext; mlx5e_media_change() local
2513 int irq; mlx5e_open_channels() local
4472 bool ext; mlx5e_create_ifp() local
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/freebsd-src/sys/dev/xen/netback/
H A Dnetback.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2009-2011 Spectra Logic Corporation
80 #include <xen/xen-os.h>
86 /*--------------------------- Compile-time Tunables --------------------------*/
88 /*---------------------------------- Macros ----------------------------------*/
94 #define XNB_SG 1 /* netback driver supports feature-sg */
95 #define XNB_GSO_TCPV4 0 /* netback driver supports feature-gso-tcpv4 */
96 #define XNB_RX_COPY 1 /* netback driver supports feature-rx-copy */
97 #define XNB_RX_FLIP 0 /* netback driver does not support feature-rx-flip */
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/freebsd-src/sys/dev/pms/freebsd/driver/ini/src/
H A Dagtiapi.c3 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
106 #define PMCoffsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
112 #define CMND_TO_CHANNEL( ccb ) ( ccb->ccb_h.path_id )
113 #define CMND_TO_TARGET( ccb ) ( ccb->ccb_h.target_id )
114 #define CMND_TO_LUN( ccb ) ( ccb->ccb_h.target_lun )
120 // Holding area for target-WWN mapping assignments on the boot line
140 tiINIGetDeviceInfo(root, dev, &pDev->devInfo); \
165 AG_LOCAL_LOCK(&pmcsc->doneLock); \
166 pccb = pmcsc->ccbDoneHead; \
169 pmcsc->ccbDoneHea
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