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/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dcortina,gemini-ethernet.txt1 Cortina Systems Gemini Ethernet Controller
4 This ethernet controller is found in the Gemini SoC family:
9 - compatible: must be "cortina,gemini-ethernet"
10 - reg: must contain the global registers and the V-bit and A-bit
12 - syscon: a phandle to the system controller
13 - #address-cells: must be specified, must be <1>
14 - #size-cells: must be specified, must be <1>
15 - ranges: should be state like this giving a 1:1 address translation
18 The subnodes represents the two ethernet ports in this device.
23 - port0: contains the resources for ethernet port 0
[all …]
H A Dcortina,gemini-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cortina Systems Gemini Ethernet Controller
10 - Linus Walleij <linus.walleij@linaro.org>
13 This ethernet controller is found in the Gemini SoC family:
19 const: cortina,gemini-ethernet
23 description: must contain the global registers and the V-bit and A-bit
26 "#address-cells":
[all …]
H A Dmarvell-orion-net.txt1 Marvell Orion/Discovery ethernet controller
4 The Marvell Discovery ethernet controller can be found on Marvell Orion SoCs
8 The Discovery ethernet controller is described with two levels of nodes. The
9 first level describes the ethernet controller itself and the second level
10 describes up to 3 ethernet port nodes within that controller. The reason for
11 the multiple levels is that the port registers are interleaved within a single
12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
20 * Ethernet controller node
23 - #address-cells: shall be 1.
[all …]
H A Dmarvell,pp2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell CN913X / Marvell Armada 375, 7K, 8K Ethernet Controller
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
14 Marvell Armada 375 Ethernet Controller (PPv2.1)
15 Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
16 Marvell CN913X Ethernet Controller (PPv2.3)
21 - marvell,armada-375-pp2
[all …]
H A Dhisilicon-hip04-net.txt1 Hisilicon hip04 Ethernet Controller
3 * Ethernet controller node
6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channe
[all...]
H A Dethernet-switch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Ethernet Switch
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vladimir Oltean <olteanv@gmail.com>
15 Ethernet switches are multi-port Ethernet controllers. Each port has
16 its own number and is represented as its own Ethernet controller.
[all …]
H A Dcavium-pip.txt1 * PIP Ethernet nexus.
3 The PIP Ethernet nexus can control several data packet input/output
6 ports might be an individual Ethernet PHY.
10 - compatible: "cavium,octeon-3860-pip"
14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
18 - #size-cells: Must be <0>.
21 - compatible: "cavium,octeon-3860-pip-interface"
25 - reg: The interface number.
27 - #address-cells: Must be <1>.
[all …]
H A Dkeystone-netcp.txt5 Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsystem with a ethernet
6 switch sub-module to send and receive packets. NetCP also includes a packet
12 Keystone II SoC's also have a 10 Gigabit Ethernet Subsystem (XGbE) which
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
14 per Ethernet port.
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/microchip/
H A Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
16 i2c0_imux: i2c-mux {
17 compatible = "i2c-mux-pinctrl";
18 #address-cell
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/net/dsa/
H A Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dmarvell,mv88e6xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
22 - enum:
23 - marvell,mv88e6085
24 - marvell,mv88e6190
25 - marvell,mv88e6250
43 - items:
44 - const: marvell,turris-mox-mv88e6085
[all …]
H A Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
14 describing a port needs to have a valid phandle referencing the internal PHY
15 it is connected to. This is because there is no N:N mapping of port and PHY
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17 the switch node and declare the phandle for the port, referencing the internal
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
[all …]
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
20 them performs packet I/O primarily through an Ethernet port of the switch
21 (which is attached to an Ethernet port of the host), rather than through
[all …]
H A Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LAN937x Ethernet Switch Series
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
[all …]
H A Ddsa-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/dsa-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic DSA Switch Port
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vladimir Oltean <olteanv@gmail.com>
15 A DSA switch port is a component of a switch that manages one MAC, and can
16 pass Ethernet frames. It can act as a stanadard Ethernet switch port, or have
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-385-clearfog-gtr-l8.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 #include "armada-385-clearfog-gtr.dtsi"
7 compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385",
11 sfp1: sfp-1 {
13 pinctrl-
[all...]
H A Darmada-381-netgear-gs110emx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 /dts-v1/;
5 #include "armada-385.dtsi"
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
14 /* So that mvebu u-boot can update the MAC addresses */
19 stdout-path = "serial0:115200n8";
22 gpio-keys {
23 compatible = "gpio-keys";
24 pinctrl-0 = <&front_button_pins>;
[all …]
H A Dorion5x-netgear-wnr854t.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include "orion5x-mv88f5181.dtsi"
11 model = "Netgear WNR854-t";
12 compatible = "netgear,wnr854t", "marvell,orion5x-8
[all...]
/freebsd-src/sys/contrib/device-tree/src/mips/cavium-octeon/
H A Docteon_3xxx.dts1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
29 marvell,reg-init =
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
[all …]
H A Docteon_68xx.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 * use. Because of this, it contains a super-set of the available
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
[all …]
/freebsd-src/share/misc/
H A Dpci_vendors5 # Date: 2024-11-25 03:15:02
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-250
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-3720-turris-mox.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi"
16 compatible = "cznic,turris-mox", "marvell,armada3720",
28 stdout-pat
[all...]
H A Dcn9130-crb.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/gpio/gpio.h>
12 stdout-path = "serial0:115200n8";
29 ap0_reg_mmc_vccq: regulator-1 {
30 compatible = "regulator-gpio";
31 regulator-name = "ap0_mmc_vccq";
32 regulator-min-microvol
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf610-zii-scu4-aib.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 // Copyright (C) 2016-2018 Zodiac Inflight Innovations
5 /dts-v1/;
10 compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610";
13 stdout-path = &uart0;
21 gpio-leds {
22 compatible = "gpio-leds";
23 pinctrl-0 = <&pinctrl_leds_debug>;
24 pinctrl-names = "default";
26 led-debug {
[all …]

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