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/freebsd-src/sys/contrib/device-tree/Bindings/crypto/
H A Dqcom,inline-crypto-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/qco
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H A Dintel,ixp4xx-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx cryptographic engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
15 (Network Processing Engine). Since it is not a device on its own
16 it is defined as a subnode of the NPE, if crypto support is
21 const: intel,ixp4xx-crypto
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H A Daspeed,ast2500-hace.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/aspeed,ast2500-hace.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ASPEED HACE hash and crypto Hardware Accelerator Engines
10 - Neal Liu <neal_liu@aspeedtech.com>
13 The Hash and Crypto Engine (HACE) is designed to accelerate the throughput
15 divided into two independently engines - Hash Engine and Crypto Engine.
20 - aspeed,ast2500-hace
21 - aspeed,ast2600-hace
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H A Dmarvell-cesa.txt4 - compatible: should be one of the following string
5 "marvell,orion-crypto"
6 "marvell,kirkwood-crypto"
7 "marvell,dove-crypto"
8 "marvell,armada-370-crypto"
9 "marvell,armada-xp-crypto"
10 "marvell,armada-375-crypto"
11 "marvell,armada-38x-crypto"
12 - reg: base physical address of the engine and length of memory mapped
14 but this representation is deprecated and marvell,crypto-srams should
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H A Dinside-secure-safexcel.txt1 Inside Secure SafeXcel cryptographic engine
4 - compatible: Should be "inside-secure,safexcel-eip197b",
5 "inside-secure,safexcel-eip197d" or
6 "inside-secure,safexcel-eip97ies".
7 - reg: Base physical address of the engine and length of memory mapped region.
8 - interrupts: Interrupt numbers for the rings and engine.
9 - interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
12 - clocks: Reference to the crypto engine clocks, the second clock is
14 - clock-names: mandatory if there is a second clock, in this case the
21 - "inside-secure,safexcel-eip197" is equivalent to
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H A Darm-cryptocell.txt1 Arm TrustZone CryptoCell cryptographic engine
4 - compatible: Should be one of -
5 "arm,cryptocell-713-ree"
6 "arm,cryptocell-703-ree"
7 "arm,cryptocell-712-ree"
8 "arm,cryptocell-710-ree"
9 "arm,cryptocell-630p-ree"
10 - reg: Base physical address of the engine and length of memory mapped region.
11 - interrupts: Interrupt number for the device.
14 - clocks: Reference to the crypto engine clock.
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H A Dqcom-qce.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/qco
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H A Dmv_cesa.txt4 - compatible: should be one of the following string
5 "marvell,orion-crypto"
6 "marvell,kirkwood-crypto"
7 "marvell,dove-crypto"
8 - reg: base physical address of the engine and length of memory mapped
10 but this representation is deprecated and marvell,crypto-srams should
12 - reg-names: "regs". Can contain an "sram" entry, but this representation
13 is deprecated and marvell,crypto-srams should be used instead
14 - interrupts: interrupt number
15 - clocks: reference to the crypto engines clocks. This property is only
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H A Daspeed,ast2600-acry.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/aspeed,ast2600-acry.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neal Liu <neal_liu@aspeedtech.com>
15 divided into two independent engines - ECC Engine and RSA Engine.
20 - aspeed,ast2600-acry
24 - description: acry base address & size
25 - description: acry sram base address & size
34 - compatible
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H A Dartpec6-crypto.txt1 Axis crypto engine with PDMA interface.
4 - compatible : Should be one of the following strings:
5 "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
6 "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
7 - reg: Base address and size for the PDMA register area.
8 - interrupts: Interrupt handle for the PDMA interrupt line.
12 crypto@f4264000 {
13 compatible = "axis,artpec6-crypto";
/freebsd-src/sys/contrib/device-tree/Bindings/firmware/
H A Dintel,ixp4xx-network-processing-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx Network Processing Engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
16 and crypto tasks. It also manages the MDIO bus to the ethernet PHYs
24 - items:
25 - const: intel,ixp4xx-network-processing-engine
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/freebsd-src/sys/dev/safe/
H A Dsafereg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
33 * Register definitions for SafeNet SafeXcel-1141 crypto device.
47 #define SAFE_PE_SRC 0x0004 /* Packet Engine Source */
48 #define SAFE_PE_DST 0x0008 /* Packet Engine Destination */
49 #define SAFE_PE_SA 0x000c /* Packet Engine SA */
50 #define SAFE_PE_LEN 0x0010 /* Packet Engine Length */
51 #define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */
52 #define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */
53 #define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */
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/freebsd-src/crypto/openssl/
H A DREADME-ENGINES.md5 ----------------
7 The ENGINE API was introduced in OpenSSL version 0.9.6 as a low level
9 primitives, most notably for integrating hardware crypto devices.
11 The ENGINE interface has its limitations and it has been superseeded
12 by the [PROVIDER API](README-PROVIDERS.md), it is deprecated in OpenSSL
14 users who need to maintain or support existing ENGINE implementations.
19 Built-in ENGINE implementations
20 -------------------------------
22 There are currently built-in ENGINE implementations for the following
23 crypto devices:
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/freebsd-src/crypto/heimdal/doc/doxyout/hcrypto/man/man3/
H A Dhcrypto_rand.31 .TH "RAND crypto functions" 3 "11 Jan 2012" "Version 1.5.2" "Heimdal crypto library" \" -*- nroff -
5 RAND crypto functions \-
34 .RI "int \fBRAND_set_rand_engine\fP (ENGINE *engine)"
48 See the \fBRAND - random number\fP for description and examples.
146 .SS "int RAND_set_rand_engine (ENGINE * engine)"
148 Set the default random method from engine.
152 \fIengine\fP use engine, if NULL is passed it, old method and engine is cleared.
197 1 on success and non-one on failure.
H A Dhcrypto_evp.31 .TH "EVP generic crypto functions" 3 "11 Jan 2012" "Version 1.5.2" "Heimdal crypto library" \" -*-
5 EVP generic crypto functions \-
103 .RI "int \fBEVP_DigestInit_ex\fP (EVP_MD_CTX *ctx, const EVP_MD *md, ENGINE *engine)"
112 …const void *data, size_t dsize, void *hash, unsigned int *hsize, const EVP_MD *md, ENGINE *engine)"
184 .RI "int \fBEVP_CipherInit_ex\fP (EVP_CIPHER_CTX *ctx, const EVP_CIPHER *c, ENGINE *engine, const v…
252 See the \fBEVP - generic crypto interface\fP for description and examples.
257 The AES-128 cipher type
261 the AES-128 EVP_CIPHER pointer.
271 The AES-128 cipher type
275 the AES-128 EVP_CIPHER pointer.
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H A Dhcrypto_rsa.31 .TH "RSA functions" 3 "11 Jan 2012" "Version 1.5.2" "Heimdal crypto library" \" -*- nroff -*-
5 RSA functions \-
13 .RI "RSA * \fBRSA_new_method\fP (ENGINE *engine)"
36 See the \fBRSA - public-key cryptography\fP for description and examples.
81 Same as \fBRSA_new_method()\fP using NULL as engine.
89 .SS "RSA* RSA_new_method (ENGINE * engine)"
91 Allocate a new RSA object using the engine, if NULL is specified as the engine, use the default RSA…
95 \fIengine\fP Specific what ENGINE RSA provider should be used.
/freebsd-src/crypto/openssl/crypto/engine/
H A Deng_rdrand.c2 * Copyright 2011-2020 The OpenSSL Project Authors. All Rights Reserved.
10 /* We need to use some engine deprecated APIs */
17 #include "crypto/engine.h"
21 #include <openssl/crypto.h>
52 static int rdrand_init(ENGINE *e) in rdrand_init()
58 static const char *engine_e_rdrand_name = "Intel RDRAND engine";
60 static int bind_helper(ENGINE *e) in bind_helper()
72 static ENGINE *ENGINE_rdrand(void) in ENGINE_rdrand()
74 ENGINE *ret = ENGINE_new(); in ENGINE_rdrand()
86 if (OPENSSL_ia32cap_P[1] & (1 << (62 - 32))) { in engine_load_rdrand_int()
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H A Deng_local.h2 * Copyright 2001-2023 The OpenSSL Project Authors. All Rights Reserved.
16 # include "crypto/engine.h"
23 * This prints the engine's pointer address, "struct" or "funct" to
25 * the file:line-number pair. The "ENGINE_REF_PRINT" statements must come
30 "engine: %p %s from %d to %d (%s:%d)\n", \
33 ? ((e)->funct_ref - (diff)) \
34 : ((e)->struct_ref - (diff))), \
35 ((isfunct) ? (e)->funct_ref : (e)->struct_ref), \
41 * callbacks in order. NB: both the "add" functions assume the engine lock to
53 DEFINE_STACK_OF(ENGINE)
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/freebsd-src/crypto/openssl/crypto/err/
H A Dopenssl.ec4 # LIBNAME PUBLIC HEADER ERROR-TABLE FILE INTERNAL HE…
7 L BN include/openssl/bnerr.h crypto/bn/bn_err.c include/cry…
8 L RSA include/openssl/rsaerr.h crypto/rsa/rsa_err.c include/cry…
9 L DH include/openssl/dherr.h crypto/dh/dh_err.c include/cry…
10 L EVP include/openssl/evperr.h crypto/evp/evp_err.c include/cry…
11 L BUF include/openssl/buffererr.h crypto/buffer/buf_err.c include/cry…
12 L OBJ include/openssl/objectserr.h crypto/objects/obj_err.c include/cry…
13 L PEM include/openssl/pemerr.h crypto/pem/pem_err.c include/cry…
14 L DSA include/openssl/dsaerr.h crypto/dsa/dsa_err.c include/cry…
15 L X509 include/openssl/x509err.h crypto/x509/x509_err.c include/cry…
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/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dmvebu-gated-clock.txt12 -----------------------------------
22 23 crypto CESA (crypto engine)
29 -----------------------------------
56 -----------------------------------
83 -----------------------------------
97 -----------------------------------
116 23 crypto CESA engine
124 -----------------------------------
134 -----------------------------------
147 15 crypto CESA engine
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/freebsd-src/share/man/man4/
H A Dccr.430 .Nd "Chelsio T6 crypto accelerator driver"
35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
49 driver provides support for the crypto accelerator engine included on
51 The driver accelerates AES-CBC, AES-CCM, AES-CT
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H A Dipsec.439 .Cd "device crypto"
65 by attaching a cryptographic checksum computed using one-way hash functions.
73 Transport mode is used to protect peer-to-peer communication between end nodes.
78 .Xr crypto 4
90 .Bl -column net.inet6.ipsec6.filtertunnel default enable
98 is controlled by a key management and policy engine,
106 The key management engine can be accessed from userland by using
113 The policy engine is controlled by an extension to the
124 which are similar to the per-packe
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/freebsd-src/sys/contrib/device-tree/Bindings/dma/
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
32 10: Multi-Channel Display Engine MCDE RX
70 48: Crypto Accelerator 1
71 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
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/freebsd-src/crypto/openssl/crypto/dh/
H A Ddh_lib.c2 * Copyright 1995-2023 The OpenSSL Project Authors. All Rights Reserved.
19 # include <openssl/engine.h>
25 #include "crypto/evp.h"
26 #include "crypto/dh.h"
29 static DH *dh_new_intern(ENGINE *engine, OSSL_LIB_CTX *libctx);
36 * to deal with which ENGINE it comes from. in DH_set_method()
39 mtmp = dh->meth; in DH_set_method()
40 if (mtmp->finish) in DH_set_method()
41 mtmp->finish(dh); in DH_set_method()
43 ENGINE_finish(dh->engine); in DH_set_method()
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/freebsd-src/crypto/openssl/crypto/conf/
H A Dconf_mall.c2 * Copyright 2002-2021 The OpenSSL Project Authors. All Rights Reserved.
10 /* We need to use some engine deprecated APIs */
14 #include <openssl/crypto.h>
19 #include <openssl/engine.h>
21 #include "crypto/rand.h"

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