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/freebsd-src/contrib/wpa/src/ap/
H A Dacs.c2 * ACS - Automatic Channel Selection module
31 * ---------
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H A Dwpa_auth_ft.c2 * hostapd - IEEE 802.11r - Fast BSS Transition
3 * Copyright (c) 2004-2018, Jouni Malinen <j@w1.fi>
58 * wpa_ft_rrb_decrypt - Decrypt FT RRB message
59 * @key: AES-SIV key for AEAD
66 * @type: Vendor-specific subtype of the RRB frame (FT_PACKET_*)
72 * Returns: 0 on success, -1 on error in wpa_ft_rrb_decrypt()
105 *plain = os_zalloc(enc_len - AES_BLOCK_SIZE); in wpa_ft_rrb_decrypt()
117 enc_len -= 2; in wpa_ft_rrb_decrypt()
123 *plain_size = enc_len - AES_BLOCK_SIZ in wpa_ft_rrb_decrypt()
788 wpa_write_mdie(struct wpa_auth_config * conf,u8 * buf,size_t len) wpa_write_mdie() argument
808 wpa_write_ftie(struct wpa_auth_config * conf,int use_sha384,const u8 * r0kh_id,size_t r0kh_id_len,const u8 * anonce,const u8 * snonce,u8 * buf,size_t len,const u8 * subelem,size_t subelem_len,int rsnxe_used) wpa_write_ftie() argument
2167 struct wpa_auth_config *conf = &sm->wpa_auth->conf; wpa_ft_gtk_subelem() local
2256 struct wpa_auth_config *conf = &sm->wpa_auth->conf; wpa_ft_igtk_subelem() local
2517 struct wpa_auth_config *conf; wpa_sm_write_assoc_resp_ies() local
2991 struct wpa_auth_config *conf = &wpa_auth->conf; wpa_ft_local_derive_pmk_r1() local
3059 struct wpa_auth_config *conf; wpa_ft_process_auth_req() local
3324 struct wpa_auth_config *conf; wpa_ft_validate_reassoc() local
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H A Dieee802_11_vht.c3 * Copyright (c) 2002-2009, Jouni Malinen <j@w1.fi>
27 struct hostapd_hw_modes *mode = hapd->iface->current_mode; in hostapd_eid_vht_capabilities()
30 if (!mode || is_6ghz_op_class(hapd->iconf->op_class)) in hostapd_eid_vht_capabilities()
33 if (mode->mode == HOSTAPD_MODE_IEEE80211G && hapd->conf->vendor_vht && in hostapd_eid_vht_capabilities()
34 mode->vht_capa in hostapd_eid_vht_capabilities()
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/freebsd-src/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-cc
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H A Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-binding
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H A Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-binding
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H A Dzynqmp-sck-kv-g-revB.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
15 /dts-v1/;
18 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
19 #address-cells = <1>;
20 #size-cells = <0>;
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H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-binding
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H A Dzynqmp-sck-kv-g-revA.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
8 * "A" – A01 board un-modified (NXP)
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/net/ti-dp83867.h>
17 #include <dt-bindings/phy/phy.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 /dts-v1/;
23 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
24 #address-cells = <1>;
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H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-cc
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H A Dzynqmp-sck-kv-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-binding
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H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-binding
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H A Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
12 /dts-v1/;
15 #include "zynqmp-clk-ccf.dtsi"
16 #include <dt-bindings/input/input.h>
17 #include <dt-binding
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H A Dzynqmp-zcu106-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-binding
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H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-binding
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H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-binding
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/freebsd-src/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
31 gpio-keys {
32 compatible = "gpio-keys";
34 switch-14 {
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H A Dzynq-zc706.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
27 stdout-path = "serial0:115200n8";
31 compatible = "usb-nop-xceiv";
32 #phy-cells = <0>;
37 ps-clk-frequency = <33333333>;
42 phy-mode = "rgmii-id";
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H A Dzynq-ebaz4205.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
6 /include/ "zynq-7000.dtsi"
10 compatible = "ebang,ebaz4205", "xlnx,zynq-7000";
23 stdout-path = "serial0:115200n8";
28 ps-clk-frequency = <33333333>;
29 fclk-enable = <8>;
34 phy-mode = "mii";
35 phy-handle = <&phy>;
38 assigned-clocks = <&clkc 18>;
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/freebsd-src/sys/net80211/
H A Dieee80211_var.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
93 * says that VHT is supported - and then this macro can be
97 ((ic)->ic_flags_ext & IEEE80211_FEXT_VHT)
100 ((ic)->ic_flags_ext & IEEE80211_FEXT_SEQNO_OFFLOAD)
102 ((ic)->ic_flags_ex
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/freebsd-src/share/man/man4/
H A Diavf.41 .\"-
2 .\" SPDX-License-Identifier: BSD-3-Clause
4 .\" Copyright (c) 2013-2018, Intel Corporation
44 .Bd -ragged -offset indent
50 .Xr loader.conf 5 :
51 .Bd -literal -offset indent
62 .Bl -bullet -compact
64 Intel\(rg Ethernet Controller E810\-C
66 Intel\(rg Ethernet Controller E810\-XXV
68 Intel\(rg Ethernet Connection E822\-C
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H A Duart.41 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
53 .Bl -tag -compact -width 0x000000
59 set RX FIFO trigger level to ``low'' (NS8250 only)
61 set RX FIF
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H A Drue.42 .\" Copyright (c) 2001-2003, Shunsuke Akiyama <akiyama@FreeBSD.org>.
36 .Bd -ragged -offset indent
47 .Xr loader.conf 5 :
48 .Bd -literal -offset indent
68 .Bl -tag -width ".Cm 10baseT/UTP"
73 .Pa /etc/rc.conf
80 .Cm full-duplex
82 .Cm half-duplex
89 .Cm full-duplex
91 .Cm half-duplex
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/freebsd-src/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_port.h2 * Copyright 2008-2013 Freescale Semiconductor Inc.
150 /** @Description BMI Rx port register map */
152 uint32_t fmbm_rcfg; /**< Rx Configuration */
153 uint32_t fmbm_rst; /**< Rx Status */
154 uint32_t fmbm_rda; /**< Rx DMA attributes*/
155 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
156 uint32_t fmbm_rfed; /**< Rx Frame End Data*/
157 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
158 uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
159 uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
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/freebsd-src/sys/contrib/alpine-hal/
H A Dal_hal_udma_config.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
284 * (in AXI beats-128b) (5b)
315 /** UDMA per queue Target-ID control configuration */
317 /* Enable usage of the Target-ID per queue according to 'tgtid' */
320 /* Enable usage of the Target-ID from the descriptor buffer address 63:48 */
323 /* Target-ID to be applied when 'queue_en' is asserted */
331 /** UDMA Target-ID control configuration */
336 /* RX queue configuration */
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