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Searched full:cmu_disp (Results 1 – 13 of 13) sorted by relevance

/freebsd-src/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433-tm2.dts19 &cmu_disp {
25 assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
27 <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
28 <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
29 <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
30 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
31 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
32 <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
33 <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
34 <&cmu_disp CLK_MOUT_DISP_PLL>,
[all …]
H A Dexynos5433-tm2e.dts19 &cmu_disp {
25 assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
27 <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
28 <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
29 <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
30 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
31 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
32 <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
33 <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
34 <&cmu_disp CLK_MOUT_DISP_PLL>,
[all …]
H A Dexynos5433.dtsi457 cmu_disp: clock-controller@13b90000 { label
952 clocks = <&cmu_disp CLK_PCLK_DECON>,
953 <&cmu_disp CLK_ACLK_DECON>,
954 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
955 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
956 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
957 <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
958 <&cmu_disp CLK_ACLK_XIU_DECON1X>,
959 <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
960 <&cmu_disp CLK_SCLK_DECON_VCL
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/display/samsung/
H A Dsamsung,exynos5433-decon.yaml103 clocks = <&cmu_disp CLK_PCLK_DECON>,
104 <&cmu_disp CLK_ACLK_DECON>,
105 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
106 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
107 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
108 <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
109 <&cmu_disp CLK_ACLK_XIU_DECON1X>,
110 <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
111 <&cmu_disp CLK_SCLK_DECON_VCLK>,
112 <&cmu_disp CLK_SCLK_DECON_ECLK>,
[all …]
H A Dsamsung,exynos-hdmi.yaml177 clocks = <&cmu_disp CLK_PCLK_HDMI>,
178 <&cmu_disp CLK_PCLK_HDMIPHY>,
179 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
180 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
181 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
182 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
183 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
184 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
186 <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
H A Dsamsung,exynos5433-mic.yaml68 clocks = <&cmu_disp CLK_PCLK_MIC0>,
69 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
/freebsd-src/sys/contrib/device-tree/Bindings/display/exynos/
H A Dexynos5433-decon.txt35 clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
36 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
37 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
38 <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
39 <&cmu_disp CLK_ACLK_XIU_DECON1X>,
40 <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
41 <&cmu_disp CLK_SCLK_DECON_VCLK>,
42 <&cmu_disp CLK_SCLK_DECON_ECLK>;
H A Dexynos-mic.txt28 clocks = <&cmu_disp CLK_PCLK_MIC0>,
29 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
/freebsd-src/sys/contrib/device-tree/Bindings/display/bridge/
H A Dsamsung,mipi-dsim.yaml249 clocks = <&cmu_disp CLK_PCLK_DSIM0>,
250 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
251 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
252 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
253 <&cmu_disp CLK_SCLK_DSIM0>;
/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dexynos5433-clock.txt24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
289 cmu_disp: clock-controller@13b90000 {
H A Dsamsung,exynos5433-clock.yaml42 # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
/freebsd-src/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dexynos5260-clk.h352 /* List Of Clocks For CMU_DISP */
H A Dexynos5433.h644 /* CMU_DISP */