| /freebsd-src/sys/contrib/device-tree/Bindings/clock/ |
| H A D | samsung,s5pv210-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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| H A D | exynos5433-clock.txt | 1 * Samsung Exynos5433 CMU (Clock Management Units)
3 The Exynos5433 clock controller generates and supplies clock to various
8 - compatible: should be one of the following.
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
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| H A D | clk-s5pv210-audss.txt | 1 * Samsung Audio Subsystem Clock Controller
3 The Samsung Audio Subsystem clock controller generates and supplies clocks
8 - compatible: should be "samsung,s5pv210-audss-clock".
9 - reg: physical base address and length of the controller's register set.
11 - #clock-cells: should be 1.
13 - clocks:
14 - hclk: AHB bus clock of the Audio Subsystem.
15 - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
17 a clock named "xxti".
18 - fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
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| H A D | samsung,s5pv210-clock.txt | 1 * Samsung S5P6442/S5PC110/S5PV210 Clock Controller
3 Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
4 controller, which generates and supplies clock to various controllers
9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
26 that they are defined using standard clock bindings with following
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| H A D | samsung,exynos-ext-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos-ext-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC external/osc/XXTI/XusbXTI clock
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Samsung SoCs require an external clock supplied through XXTI or XusbXTI pins.
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| H A D | samsung,s5pv210-audss-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5Pv210 SoC Audio SubSystem clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
17 include/dt-bindings/clock/s5pv210-audss.h header.
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| H A D | exynos5410-clock.txt | 1 * Samsung Exynos5410 Clock Controller
3 The Exynos5410 clock controller generates and supplies clock to various
8 - compatible: should be "samsung,exynos5410-clock"
10 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
15 - clocks: should contain an entry specifying the root clock from external
16 oscillator supplied through XXTI or XusbXTI pin. This clock should be
17 defined using standard clock bindings with "fin_pll" clock-output-name.
18 That clock is being passed internally to the 9 PLLs.
21 dt-bindings/clock/exynos5410.h header and can be used in device
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| H A D | samsung,exynos5410-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5410 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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| H A D | samsung,exynos5433-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5433 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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| H A D | exynos7-clock.txt | 1 * Samsung Exynos7 Clock Controller
3 Exynos7 clock controller has various blocks which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos7-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
22 Required Properties for Clock Controller:
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| H A D | exynos5260-clock.txt | 1 * Samsung Exynos5260 Clock Controller
3 Exynos5260 has 13 clock controllers which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos5260-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
21 - "xrtcxti" - input clock from XRTCXTI
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| H A D | samsung,exynos7-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos7 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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| /freebsd-src/sys/contrib/device-tree/src/arm64/exynos/ |
| H A D | exynos5433.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cell
44 xxti: clock { global() label
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| /freebsd-src/sys/contrib/device-tree/src/arm/samsung/ |
| H A D | s5pv210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
19 #include <dt-bindings/clock/s5pv210.h>
20 #include <dt-bindings/clock/s5pv210-audss.h>
23 #address-cell
55 xxti: oscillator-0 { global() label
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| H A D | exynos4412-tiny4412.dts | 1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/leds/common.h>
25 stdout-path = &serial_0;
34 compatible = "gpio-leds";
40 default-state = "off";
41 linux,default-trigger = "heartbeat";
47 default-state = "off";
53 default-state = "off";
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| H A D | exynos4412-smdk4412.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include "exynos-mfc-reserved-memory.dtsi"
31 stdout-path = "serial1:115200n8";
34 fixed-rat
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| H A D | exynos4210-smdkv310.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
14 /dts-v1/;
16 #include <dt-bindings/gpio/gpio.h>
17 #include "exynos-mfc-reserved-memor
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| H A D | exynos5260-xyref5260.dts | 1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
27 stdout-path = "serial2:115200n8";
30 fin_pll: xxti {
31 compatible = "fixed-clock";
32 clock-frequency = <24000000>;
33 clock-output-names = "fin_pll";
34 #clock-cells = <0>;
37 ioclk_pcm: clock-pcm-ext {
38 compatible = "fixed-clock";
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| H A D | exynos4210-origen.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
14 /dts-v1/;
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/leds/common.h>
19 #include "exynos-mfc-reserved-memory.dtsi"
40 stdout-path = "serial2:115200n8";
43 mmc_reg: voltage-regulator {
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| H A D | exynos5250-smdk5250.dts | 1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/clock/maxim,max77686.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
31 stdout-path = "serial2:115200n8";
34 vdd: fixed-regulator-vdd {
35 compatible = "regulator-fixed";
36 regulator-name = "vdd-supply";
37 regulator-min-microvolt = <1800000>;
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| H A D | exynos4412-odroid-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
22 stdout-path = &serial_1;
26 compatible = "samsung,secure-firmware";
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| H A D | exynos5410-smdk5410.dts | 1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
27 stdout-path = "serial2:115200n8";
30 fin_pll: xxti {
31 compatible = "fixed-clock";
32 clock-frequency = <24000000>;
33 clock-output-names = "fin_pll";
34 #clock-cells = <0>;
37 pmic_ap_clk: pmic-ap-clk {
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| H A D | exynos4210-trats.dts | 1 // SPDX-License-Identifier: GPL-2.0
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
37 stdout-path = "serial2:115200n8";
40 vemmc_reg: regulator-0 {
41 compatible = "regulator-fixed";
42 regulator-name = "VMEM_VDD_2.8V";
43 regulator-min-microvolt = <2800000>;
44 regulator-max-microvolt = <2800000>;
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| H A D | exynos4412-itop-scp-core.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
17 #include "exynos4412-ppmu-common.dtsi"
18 #include "exynos-mfc-reserved-memory.dtsi"
31 compatible = "samsung,secure-firmware";
35 fixed-rate-clocks {
36 xxti {
37 compatible = "samsung,clock-xxti";
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| /freebsd-src/sys/contrib/device-tree/Bindings/display/samsung/ |
| H A D | samsung,exynos-hdmi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-hdmi
19 - samsung,exynos4212-hdmi
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