| /freebsd-src/sys/contrib/device-tree/Bindings/clock/ |
| H A D | xgene.txt | 1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
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| H A D | moxa,moxart-clock.txt | 1 Device Tree Clock bindings for arch-moxart
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - compatible : Must be "moxa,moxart-pll-clock"
15 - #clock-cells : Should be 0
16 - reg : Should contain registers location and length
17 - clocks : Should contain phandle + clock-specifier for the parent clock
20 - clock-output-names : Should contain clock name
26 - compatible : Must be "moxa,moxart-apb-clock"
27 - #clock-cells : Should be 0
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| /freebsd-src/sys/dev/clk/ |
| H A D | clk.c | 1 /*-
51 SYSCTL_NODE(_hw, OID_AUTO, clock, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
54 MALLOC_DEFINE(M_CLOCK, "clocks", "Clock framework");
64 /* Default clock methods. */
73 * Clock controller methods.
87 * Clock node - basic element for modeling SOC clock graph. It holds the clock
88 * provider's data about the clock, and the links for the clock's membership in
94 /* Clock nodes topology. */
95 struct clkdom *clkdom; /* Owning clock domain */
102 int parent_idx; /* Parent index or -1 */
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| /freebsd-src/sys/contrib/device-tree/src/arm/samsung/ |
| H A D | exynos4412-odroid-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
22 stdout-path = &serial_1;
26 compatible = "samsung,secure-firmware";
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| H A D | exynos4210-trats.dts | 1 // SPDX-License-Identifier: GPL-2.0
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
37 stdout-path = "serial2:115200n8";
40 vemmc_reg: regulator-0 {
41 compatible = "regulator-fixed";
42 regulator-name = "VMEM_VDD_2.8V";
43 regulator-min-microvolt = <2800000>;
44 regulator-max-microvolt = <2800000>;
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| H A D | exynos4210-universal_c210.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
39 fixed-rate-clocks {
41 compatible = "samsung,clock-xxti";
42 clock-frequency = <0>;
46 compatible = "samsung,clock-xusbxti";
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| H A D | exynos4210-i9100.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree
11 /dts-v1/;
13 #include "exynos4412-ppmu-common.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/linux-event-codes.h>
19 model = "Samsung Galaxy S2 (GT-I9100)";
21 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
38 vemmc_reg: regulator-0 {
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| H A D | exynos4412-midas.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
12 /dts-v1/;
14 #include "exynos4412-ppmu-common.dtsi"
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/clock/maxim,max77686.h>
20 #include "exynos-pinctrl.h"
34 stdout-path = &serial_2;
38 compatible = "samsung,secure-firmware";
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| H A D | exynos5410-odroidxu.dts | 1 // SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/sound/samsung-i2s.h>
16 #include "exynos54xx-odroidxu-leds.dtsi"
20 compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5";
34 stdout-path = "serial2:115200n8";
38 pinctrl-0 = <&emmc_nrst_pin>;
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| /freebsd-src/sys/contrib/device-tree/Bindings/clock/ti/davinci/ |
| H A D | pll.txt | 5 an multiplexers for various clock signals.
8 - compatible: shall be one of:
9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
11 - reg: physical base address and size of the controller's register area.
12 - clocks: phandles corresponding to the clock names
13 - clock-names: names of the clock sources - depends on compatible string
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
15 - for "ti,da850-pll1", shall be "clksrc"
18 - ti,clkmode-square-wave: Indicates that the board is supplying a square
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| /freebsd-src/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/qe/ |
| H A D | ucc.txt | 4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
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| /freebsd-src/sys/contrib/device-tree/Bindings/display/ |
| H A D | allwinner,sun8i-r40-tcon-top.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
17 encoder clock source and contains additional TV TCON and DSI gates.
22 / [0] TCON-LCD0
25 \ / [1] TCON-LCD1 - LCD1/LVDS1
26 TCON-TOP
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| /freebsd-src/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | rohm,bd70528-pmic.txt | 3 BD70528MWV is an ultra-low quiescent current general purpose, single-chip,
4 power management IC for battery-powered portable devices. The IC
5 integrates 3 ultra-low current consumption buck converters, 3 LDOs and 2
6 LED Drivers. Also included are 4 GPIOs, a real-time clock (RTC), a 32kHz
7 clock gate, high-accuracy VREF for use with an external ADC, flexible
8 dual-input power path, 10 bit SAR ADC for battery temperature monitor and
12 - compatible : Should be "rohm,bd70528"
13 - reg : I2C slave address.
14 - interrupts : The interrupt line the device is connected to.
15 - interrupt-controller : To indicate BD70528 acts as an interrupt controller.
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| H A D | rockchip,rk817.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schema
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| H A D | rk808.txt | 11 - compatible: "rockchip,rk805"
12 - compatible: "rockchip,rk808"
13 - compatible: "rockchip,rk809"
14 - compatible: "rockchip,rk817"
15 - compatible: "rockchip,rk818"
16 - reg: I2C slave address
17 - interrupts: the interrupt outputs of the controller.
18 - #clock-cells: from common clock binding; shall be set to 1 (multiple clock
19 outputs). See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
22 - clock-output-names: From common clock binding to override the
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| H A D | rockchip,rk809.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Zhong <zyw@rock-chips.com>
11 - Zhang Qing <zhangqing@rock-chips.com>
20 - rockchip,rk809
28 '#clock-cells':
30 See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
34 clock-output-names:
36 From common clock binding to override the default output clock name.
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| H A D | rockchip,rk805.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schema
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| /freebsd-src/sys/arm/ti/twl/ |
| H A D | twl_clks.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
43 * external-clocks = "name1", "state1",
47 * Each override should be a pair, the first entry is the name of the clock
97 const char *name; member
119 char name[TWL_CLKS_MAX_NAMELEN]; member
120 uint8_t sub_dev; /* the sub-device number for the clock */
121 uint8_t reg_off; /* register base address of the clock */
135 #define TWL_CLKS_XLOCK(_sc) sx_xlock(&(_sc)->sc_sx)
136 #define TWL_CLKS_XUNLOCK(_sc) sx_xunlock(&(_sc)->sc_sx)
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| /freebsd-src/sys/contrib/device-tree/src/arm64/amlogic/ |
| H A D | meson-g12.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-binding
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| /freebsd-src/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/ |
| H A D | network.txt | 4 - fsl,cpm1-scc-enet
5 - fsl,cpm2-scc-enet
6 - fsl,cpm1-fec-enet
7 - fsl,cpm2-fcc-enet (third resource is GFEMR)
8 - fsl,qe-enet
13 compatible = "fsl,mpc8272-fcc-enet",
14 "fsl,cpm2-fcc-enet";
16 local-mac-address = [ 00 00 00 00 00 00 ];
18 interrupt-parent = <&PIC>;
19 phy-handle = <&PHY0>;
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| /freebsd-src/sys/contrib/device-tree/Bindings/net/ |
| H A D | snps,dwc-qos-ethernet.txt | 13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
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| /freebsd-src/sys/dev/sound/pci/ |
| H A D | hdsp.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com>
5 * Copyright (c) 2023-2024 Florian Walpen <dev@submerge.ch>
112 snd_mtxlock(sc->lock); in hdsp_intr()
116 if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) in hdsp_intr()
121 if (scp->i in hdsp_intr()
320 struct hdsp_clock_source *clock_table, *clock; hdsp_sysctl_clock_preference() local
395 struct hdsp_clock_source *clock_table, *clock; hdsp_sysctl_clock_source() local
435 struct hdsp_clock_source *clock_table, *clock; hdsp_sysctl_clock_list() local
512 struct hdsp_clock_source *clock_table, *clock; hdsp_sysctl_sync_status() local
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| H A D | hdspe.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com>
5 * Copyright (c) 2023-2024 Florian Walpen <dev@submerge.ch>
122 snd_mtxlock(sc->lock); in hdspe_intr()
126 if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) in hdspe_intr()
131 if (scp->i in hdspe_intr()
312 struct hdspe_clock_source *clock_table, *clock; hdspe_sysctl_clock_preference() local
363 struct hdspe_clock_source *clock_table, *clock; hdspe_sysctl_clock_source() local
403 struct hdspe_clock_source *clock_table, *clock; hdspe_sysctl_clock_list() local
432 struct hdspe_clock_source *clock_table, *clock; hdspe_sysctl_sync_status() local
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| /freebsd-src/contrib/ntp/ntpd/ |
| H A D | ntpd.1ntpdmdoc | 4 .\" EDIT THIS FILE WITH CAUTION (ntpd-opts.mdoc)
6 .\" It has been AutoGen-ed May 25, 2024 at 12:03:54 AM by AutoGen 5.18.16
7 .\" From the definitions ntpd-opts.def
8 .\" and the template file agmdoc-cmd.tpl
9 .Sh NAME
17 .Op Fl \-option\-name Ns Oo Oo Ns "=| " Oc Ns Ar value Oc
27 Network Time Protocol (NTP) version 4, as defined by RFC\-5905,
29 version 3, as defined by RFC\-1305, and versions 1
30 and 2, as defined by RFC\-1059 and RFC\-1119, respectively.
34 utility does most computations in 64\-bit floating point
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| /freebsd-src/usr.sbin/ntp/doc/ |
| H A D | ntpd.8 | |