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/freebsd-src/sys/contrib/device-tree/Bindings/dma/
H A Dqcom_hidma_mgmt.txt14 instance can use like maximum read/write request and number of bytes to
15 read/write in a single burst.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
34 - max-read-transactions: This value is how many times a read burst is
36 - channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
[all …]
H A Drenesas,nbpfaxi.txt1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
28 than using the maximum burst size allowed by the hardware's buffer size.
29 - max-burst-mem-write: limit burst size for memory writes
31 than using the maximum burst size allowed by the hardware's buffer size.
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
[all …]
H A Dintel,ldma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
[all …]
H A Domap-gpmc.txt7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
[all …]
H A Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
25 8: Synchronous read synchronous write PSRAM.
26 9: Synchronous read asynchronous write PSRAM.
27 10: Synchronous read synchronous write NOR.
[all …]
H A Dmvebu-devbus.txt9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
37 - devbus,turn-off-ps: Defines the time during which the controller does not
[all …]
/freebsd-src/sys/contrib/alpine-hal/
H A Dal_hal_udma_regs_s2m.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
59 /* [0x0] Data write master configuration */
61 /* [0x4] Data write master configuration */
67 /* [0x10] Completion write master configuration */
69 /* [0x14] Completion write master configuration */
71 /* [0x18] Data write master configuration */
75 /* [0x20] Completion descriptors write master configuration */
79 /* [0x28] AXI outstanding write configuration */
86 * 00 - No pending tasks
[all …]
H A Dal_hal_udma_config.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
81 uint8_t burst; member
95 uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */
108 uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */
137 /* in one burst (5b) */
139 uint8_t min_burst_above_thr; /* min burst size when fifo above
142 uint8_t min_burst_below_thr; /* min burst size when fifo below
168 uint8_t min_burst_above_thr; /* min burst size when fifo above
[all …]
H A Dal_hal_udma_regs_m2s.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
59 /* [0x0] Completion write master configuration */
61 /* [0x4] Completion write master configuration */
75 /* [0x20] Descriptors write master configuration (completion) */
84 * 00 - No pending tasks
98 * 0 - Log is enabled.
99 * 1 - Log is masked.
173 /* [0x10] Data burst read configuration */
213 * 0 - Rate limit is active.
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap3-gta04a5one.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
6 #include "omap3-gta04a5.dts"
13 gpmc_pins: gpmc-pins {
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
[all …]
H A Domap3-igep.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
19 stdout-path = &uart3;
23 compatible = "ti,omap-twl4030";
28 vdd33: regulator-vdd33 {
29 compatible = "regulator-fixed";
30 regulator-name = "vdd33";
31 regulator-always-on;
37 gpmc_pins: gpmc-pins {
38 pinctrl-single,pins = <
[all …]
H A Domap3-n950-n9.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff)
13 cpu0-supply = <&vcc>;
23 compatible = "regulator-fixed";
24 regulator-name = "VEMMC";
25 regulator-min-microvolt = <2900000>;
26 regulator-max-microvolt = <2900000>;
28 startup-delay-us = <150>;
29 enable-active-high;
33 compatible = "regulator-fixed";
[all …]
/freebsd-src/sys/contrib/openzfs/module/zfs/
H A Dzfs_ratelimit.c9 * or https://opensource.org/licenses/CDDL-1.0.
32 * burst: Number to allow in an interval before rate limiting
36 zfs_ratelimit_init(zfs_ratelimit_t *rl, unsigned int *burst, in zfs_ratelimit_init() argument
39 rl->count = 0; in zfs_ratelimit_init()
40 rl->start = 0; in zfs_ratelimit_init()
41 rl->interval = interval; in zfs_ratelimit_init()
42 rl->burst = burst; in zfs_ratelimit_init()
43 mutex_init(&rl->lock, NULL, MUTEX_DEFAULT, NULL); in zfs_ratelimit_init()
54 mutex_destroy(&rl->lock); in zfs_ratelimit_fini()
58 * Re-implementation of the kernel's __ratelimit() function
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jos
[all...]
/freebsd-src/sys/contrib/openzfs/include/sys/
H A Dzil_impl.h9 * or https://opensource.org/licenses/CDDL-1.0.
58 * After the lwb's write zio completes, it transitions into the "write
61 * "issued" to "write done", and then from "write done" to "flush done",
94 * Log write block (lwb)
113 char *lwb_buf; /* log write buffer */
116 zio_t *lwb_root_zio; /* root zio for lwb write and flushes */
118 uint64_t lwb_issued_txg; /* the txg when the write is issued */
121 list_node_t lwb_node; /* zilog->zl_lwb_list linkage */
125 avl_tree_t lwb_vdev_tree; /* vdevs to flush after lwb write */
177 * we've touched so we know which ones need a write cache flush at the end.
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/bus/
H A Dqcom,ebi2.txt4 external memory (such as NAND or other memory-mapped peripherals) whereas
10 NOR flash memories), WE (write enable). This on top of 6 different chip selects
18 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
31 The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/bonnell/
H A Dother.json139 "BriefDescription": "Burst read bus transactions.",
147 "BriefDescription": "Burst read bus transactions.",
155 "BriefDescription": "Burst (full cache-line) bus transactions.",
163 "BriefDescription": "Burst (full cache-line) bus transactions.",
187 "BriefDescription": "Instruction-fetch bus transactions.",
195 "BriefDescription": "Instruction-fetch bus transactions.",
267 "BriefDescription": "Partial write bus transaction.",
275 "BriefDescription": "Partial write bus transaction.",
331 "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
/freebsd-src/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_freebsd_inc.h15 #define AH_SUPPORT_WRITE_EEPROM 0 /* EEPROM write support */
59 #define OS_ATOMIC_DEC(a) (*a)--
99 u_int32_t rp_numpulses ; /* Num of pulses in radar burst */
101 u_int32_t rp_pulsefreq; /* Frequency of pulses in burst */
102 u_int32_t rp_max_pulsefreq; /* Frequency of pulses in burst */
105 matched filter (single-sided) in usecs */
122 u_int32_t rp_numpulses; /* Num of pulses in radar burst */
124 u_int32_t rp_min_pulsefreq; /* Frequency of pulses in burst */
125 u_int32_t rp_max_pulsefreq; /* Frequency of pulses in burst */
128 matched filter (single-sided) in usecs */
[all …]
/freebsd-src/sys/dev/acpica/
H A Dacpi_ec.c1 /*-
2 * Copyright (c) 2003-2007 Nate Lawson
55 * -----------
68 * ----------
72 * +-+-+-+-+-+-+-+-+
74 * +-+-+-+-+-+-+-+-+
76 * | | | | | | | +- Output Buffer Full?
77 * | | | | | | +--- Input Buffer Full?
78 * | | | | | +----- <reserved>
79 * | | | | +------- Data Register is Command Byte?
[all …]
/freebsd-src/sys/dev/tpm/
H A Dtpm.c3 * Copyright (c) 2009, 2010 Hans-Joerg Hoexer
49 #define IRQUNK -1
83 #define TPM_INTF_INT_LEVEL_LOW 0x0010 /* level-low ints supported */
84 #define TPM_INTF_INT_LEVEL_HIGH 0x0008 /* level-high ints supported */
85 #define TPM_INTF_LOCALITY_CHANGE_INT 0x0004 /* locality-change int (mb 1) */
95 #define TPM_STS_BMASK 0x00ffff00 /* ro io burst size */
128 ((struct tpm_softc *)dev->si_drv1)
206 sc->mem_rid = 0; in tpm_attach()
207 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, in tpm_attach()
209 if (sc->mem_res == NULL) in tpm_attach()
[all …]
/freebsd-src/sys/dev/mmc/host/
H A Ddwmmc_reg.h1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
46 #define SDMMC_CLKENA_LP (1 << 16) /* Low-power mode */
56 #define SDMMC_INTMASK_EBE (1 << 15) /* End-bit error */
58 #define SDMMC_INTMASK_SBE (1 << 13) /* Start-bit error */
59 #define SDMMC_INTMASK_HLE (1 << 12) /* Hardware locked write err */
82 #define SDMMC_CMD_DATA_WRITE (1 << 10) /* Write to card */
98 #define SDMMC_FIFOTH_MSIZE_S 28 /* Burst size of multiple transaction */
102 #define SDMMC_WRTPRT 0x54 /* Write Protect Register */
104 #define SDMMC_TBBCNT 0x60 /* Transferred Host to BIU-FIFO Byte Count */
[all …]
/freebsd-src/sys/dev/igc/
H A Digc_i225.c1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
22 * igc_init_nvm_params_i225 - Init NVM func ptrs.
27 struct igc_nvm_info *nvm = &hw->nvm; in igc_init_nvm_params_i225()
36 * Added to a constant, "size" becomes the left-shift value in igc_init_nvm_params_i225()
47 nvm->word_size = 1 << size; in igc_init_nvm_params_i225()
48 nvm->opcode_bits = 8; in igc_init_nvm_params_i225()
49 nvm->delay_usec = 1; in igc_init_nvm_params_i225()
50 nvm->type = igc_nvm_eeprom_spi; in igc_init_nvm_params_i225()
53 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; in igc_init_nvm_params_i225()
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/mtd/
H A Dgpmc-nor.txt8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 - bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
12 16-bit devices and so must be either 1 or 2 bytes.
13 - compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
14 - gpmc,cs-on-ns: Chip-select assertion time
15 - gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
16 - gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
17 - gpmc,oe-on-ns: Output-enable assertion time
18 - gpmc,oe-off-ns: Output-enable de-assertion time
19 - gpmc,we-on-ns Write-enable assertion time
[all …]

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