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/freebsd-src/sys/contrib/device-tree/Bindings/spi/
H A Dbrcm,spi-bcm-qspi.txt4 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits
9 io with 3-byte and 4-byte addressing support.
18 - #address-cells:
21 - #size-cells:
24 - compatible:
26 "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs
27 "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI
29 "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
31 "brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
33 "brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
[all …]
H A Dbrcm,spi-bcm-qspi.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
20 io with 3-byte and 4-byte addressing support.
28 - $ref: spi-controller.yaml#
33 - description: Second Instance of MSPI BRCMSTB SoCs
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dbrcm,iproc-clocks.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <rjui@broadcom.com>
11 - Scott Branden <sbranden@broadcom.com>
25 - brcm,bcm63138-armpll
26 - brcm,cygnus-armpll
27 - brcm,cygnus-genpll
28 - brcm,cygnus-lcpll0
[all …]
H A Dbrcm,iproc-clocks.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - compatible:
14 Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
15 Cygnus has a compatible string of "brcm,cygnus-genpll"
17 - #clock-cells:
20 - reg:
24 - clocks:
28 - clock-output-names:
34 #clock-cells = <0>;
35 compatible = "fixed-clock";
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm-nsp.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "brcm,nsp";
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
[all …]
H A Dbcm5301x.dtsi9 #include "bcm-ns.dtsi"
12 mpcore-bus@19000000 {
14 #clock-cells = <0>;
15 compatible = "brcm,nsp-armpll";
21 compatible = "arm,cortex-a9-twd-wdt";
30 #address-cells = <1>;
31 #size-cells = <1>;
35 #clock-cells = <0>;
36 compatible = "fixed-clock";
37 clock-frequency = <25000000>;
[all …]
H A Dbcm958625-meraki-mx64-a0.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
8 /dts-v1/;
10 #include "bcm958625-meraki-kingpin.dtsi"
11 #include "bcm-nsp-ax.dtsi"
15 compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp";
18 stdout-path = "serial0:115200n8";
H A Dbcm958625-meraki-mx64w-a0.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
8 /dts-v1/;
10 #include "bcm958625-meraki-kingpin.dtsi"
11 #include "bcm-nsp-ax.dtsi"
15 compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp";
18 stdout-path = "serial0:115200n8";
H A Dbcm958522er.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958522er", "brcm,bcm58522", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
81 nand-on-flash-bbt;
83 #address-cells = <1>;
[all …]
H A Dbcm958525er.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958525er", "brcm,bcm58525", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
81 nand-on-flash-bbt;
83 #address-cells = <1>;
[all …]
H A Dbcm4708.dtsi5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
20 stdout-path = "serial0:115200n8";
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "brcm,bcm-nsp-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
39 secondary-boot-reg = <0xffff0400>;
H A Dbcm958622hr.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958622hr", "brcm,bcm58622", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
85 nand-on-flash-bbt;
87 #address-cells = <1>;
[all …]
H A Dbcm958525xmc.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958525xmc", "brcm,bcm58525", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
76 temperature-sensor@4c {
97 nand-on-flash-bbt;
[all …]
H A Dbcm958625hr.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958625hr", "brcm,bcm58625", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
60 i2c-bus = <&i2c0>;
61 mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
[all …]
H A Dbcm958623hr.dts33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958623hr", "brcm,bcm58623", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
85 nand-on-flash-bbt;
87 #address-cells = <1>;
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/rng/
H A Dbrcm,bcm2835.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stefan Wahren <stefan.wahren@i2se.com>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Herbert Xu <herbert@gondor.apana.org.au>
17 - brcm,bcm2835-rng
18 - brcm,bcm-nsp-rng
19 - brcm,bcm5301x-rng
20 - brcm,bcm6368-rng
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/bcm/
H A Dbrcm,nsp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/bcm/brcm,nsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
18 - Ray Jui <rjui@broadcom.com>
19 - Scott Branden <sbranden@broadcom.com>
26 - description: BCM58522 based boards
28 - enum:
29 - brcm,bcm958522er
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/mfd/
H A Dbrcm,cru.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/interconnect/
H A Dqcom,sc7280-rpmh.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sc7280-rpm
[all...]
H A Dqcom,x1e80100-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,x1e80100-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on X1E80100
10 - Rajendra Nayak <quic_rjendra@quicinc.com>
11 - Abel Vesa <abel.vesa@linaro.org>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
16 able to communicate with the BCM through the Resource State Coordinator (RSC)
21 See also:: include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
[all …]
H A Dqcom,sm8550-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8550-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8550
10 - Abel Vesa <abel.vesa@linaro.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
16 able to communicate with the BCM through the Resource State Coordinator (RSC)
21 See also:: include/dt-bindings/interconnect/qcom,sm8550-rpmh.h
[all …]
H A Dqcom,sm8650-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8650-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8650
10 - Abel Vesa <abel.vesa@linaro.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
16 able to communicate with the BCM through the Resource State Coordinator (RSC)
21 See also:: include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
[all …]
H A Dqcom,sm8450-rpmh.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8450-rpm
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/phy/
H A Dbcm-ns-usb2-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/bcm-ns-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Rafał Miłecki <rafal@milecki.pl>
18 const: brcm,ns-usb2-phy
22 - maxItems: 1
24 - maxItems: 1
28 reg-names:
30 - const: dmu
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/pinctrl/
H A Dbrcm,iproc-gpio.txt5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
23 - reg:
[all …]

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